Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA | Approximate power and area values for a 1-bit SRAM cell.
There are 1 messages in this thread.
You are currently looking at messages 0 to 1.
Approximate power and area values for a 1-bit SRAM cell. - 2006-02-18 16:02:00
Hi, Can some one give an insight about the *approximate* values of power and area consumption of a 1-bit SRAM cell for 0.13 micron technology. We need to approximate the area of 4-input LUT and our synthesis tool does not support SRAM standard cells in its library. It synthesises a DFF as memory element. How far will it be sensible to calculate the area of 4-input LUT through the tool and subsitute the dff's area by a SRAM cell's area ? Kindly help. Thanks.
