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Comp.Arch.FPGA | SDRAM Reading problem
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SDRAM Reading problem - raju_lingala - 2006-02-20 15:02:00
Hi all, I am new to this group and i am facing one problem regardingreading from the sdram. Actually I am accessing sdram indirectly through CPU. So I am writingwrite data into the fpga registers and set the wr_start bit, aftercompleting the write operation wr_start bit will be cleared indicatingwrite has completed. To verify the data written to sdram i am setting theread_start and reading immediately and the data is correct. But if i readafter sometime the data i am getting is FFFF FFFF (two 16 bit sdrams). Iam operating sdram (SDR sdram) at 125 Mhz. Is this because of auto refresh is not done properly? But i am accessing 3sdrams on the board. Sometime one the sdram works and remaining fails. Can anyone has idea? or require more info to answer. Thanks in advance.______________________________
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