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Comp.Arch.FPGA | How to interface ASIC on a PCB and and an FPGA

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

How to interface ASIC on a PCB and and an FPGA - Biswajit Mishra - 2006-03-06 05:08:00

Hi,
I have a custom ASIC and I would like to interface this with my XUP V2P 
(Xilinx
VII Pro) board. I am new to using the Xilinx boards. Please suggest a simple
way to generate a clock from the FPGA and few synchronised control signals 
with
this clock. I have to feed the clock and the control signals to ASIC. 
Basically
the FPGA is acting as a controller for the ASIC (The ASIC is on a simple 
PCB, The ASIC is implemented using 0.12 micron libraries and run at 1.2 V).

Here is how my perceived test setup looks like.

FPGA XUP V2P -->  Clk and Control Signals for ASIC -->  ASIC | --> 
Oscilloscope for tracking signals

Please suggest a simpler method as I am just starting a project with the 
FPGA.
I would be very thankful for any help.


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Re: How to interface ASIC on a PCB and and an FPGA - 2006-03-06 06:01:00

Hi,
i think u should clkout pin for verification.

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Re: How to interface ASIC on a PCB and and an FPGA - Alex - 2006-03-06 07:53:00

Hi.

For the begining, the approach you described is fine (later you might want  
to read out the signals from
your asic to the fpga, process them, etc.). From engineering point of  
view, just be careful with signal driving.
I.e. use dedicated pins for clocks (check the xilinx manual), check the  
impidance of the connection path (in some cases you
might want to place a pulling resistor, etc. etc.).
Regards
Alex


> Hi,
> I have a custom ASIC and I would like to interface this with my XUP V2P
> (Xilinx
> VII Pro) board. I am new to using the Xilinx boards. Please suggest a  
> simple
> way to generate a clock from the FPGA and few synchronised control  
> signals
> with
> this clock. I have to feed the clock and the control signals to ASIC.
> Basically
> the FPGA is acting as a controller for the ASIC (The ASIC is on a simple
> PCB, The ASIC is implemented using 0.12 micron libraries and run at 1.2  
> V).
>
> Here is how my perceived test setup looks like.
>
> FPGA XUP V2P -->  Clk and Control Signals for ASIC -->  ASIC | -->
> Oscilloscope for tracking signals
>
> Please suggest a simpler method as I am just starting a project with the
> FPGA.
> I would be very thankful for any help.
>
>
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