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Comp.Arch.FPGA | How to write compact DFF chain?

There are 4 messages in this thread.

You are currently looking at messages 0 to 4.

How to write compact DFF chain? - Davy - 2006-03-24 21:01:00

Hi all,

Sometimes I have to write long DFF chain like below:

//------code--------------
...
reg [7:0] DFF0,DFF1,DFF2,...DFF50;

always@(posedge clk)
    if(rst)
    begin
        DFF0 <= 0;
        ...
        DFF50 <= 0;
    end
    else
    begin
        DFF0 <= INPUT;
        ...
        DFF50 <= DFF49;
    end

//------code end-----------
It's too long, is there any good compact style?

Any suggestions will be appreciated!
Best regards,
Davy



Re: How to write compact DFF chain? - Andrew Holme - 2006-03-25 03:04:00

"Davy" <z...@gmail.com> wrote in message 
news:1...@i39g2000cwa.googlegroups.com...
> Hi all,
>
> Sometimes I have to write long DFF chain like below:
>
> //------code--------------
> ...
> reg [7:0] DFF0,DFF1,DFF2,...DFF50;
>
> always@(posedge clk)
>    if(rst)
>    begin
>        DFF0 <= 0;
>        ...
>        DFF50 <= 0;
>    end
>    else
>    begin
>        DFF0 <= INPUT;
>        ...
>        DFF50 <= DFF49;
>    end
>
> //------code end-----------
> It's too long, is there any good compact style?

Can't you declare it as :

reg [7:0] DFF[0:50];

and then use for loops with the loop counter declared as an integer?  I 
believe this is synthesizeable.  Am I right?
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Re: How to write compact DFF chain? - Michael - 2006-03-25 04:01:00

You could make another verilog95 way:

reg [8*51-1:0] DFFs;
wire [7:0] DFF0,DFF1,DFF2,...DFF50;
assign {DFF50, DFF49, ..., DFF0} = DFFs;

always @(posedge clk) begin
  if(rst) DFFs <= {51{8'h00}};
  else begin
    DFFs <= DFFs << 8;
    DFFs[7:0] <= INPUT;
  end
end

Of course you can omit assigning and use only required bits from vector
DFFs.

Re: How to write compact DFF chain? - Thomas Stanka - 2006-03-28 01:24:00

Xpost from OP,  FUp2 comp.lang.vhdl

Davy schrieb:

> Sometimes I have to write long DFF chain like below:

In VHDL you would write

if reset_active then
  DFF <= (others =>'0');
 elsif rising_edge(Clk)
  DFF <= DFF( xxx downto 0) & input;
end if

If you don't like to change to VHDL than you should avoid posting in
the VHDL-group.

bye Thomas