I hope I'm posting it in the right groups.  I've
been designing for a
while, but with minimal JTAG knowledge.

Q: Can I use JTAG interface to verify what I wrote into the SRAM,
instead of the traditional
read-back method?

My setup and the reason for wanting to do it this way is :
An FPGA interfaces to a sync SRAM (QDR with separate write/read port).
The FPGA can write to the SRAM
using the processor interface, but does not have the read-back
capability, because the read port from the SRAM goes elsewhere (no
read-back capability there, either).  Why do it this way?  So that the
each of the write/read data bus is point-to-point, without stubs on the
board (150+Mhz).  I could therotically bring the read bus back into the
FPGA, then send it out again, but I'm fairly pin-limited.  There are
several SRAM interfaces, so whatever I do for each SRAM gets multipled
by N.  So, what I'd like to do is load the SRAM in a conventional
manner, then test it via the JTAG interface.  The amount of time it
takes to verify doesn't matter.

The SRAM I'm thinking of using is Cypress, will be running it at
150+Mhz, and the device supports these JTAG instructions : EXTEST,
IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported,
actually).  Looking at this, it looks like I need to use the FPGA to
supply the read controls at a slower rate, to match JTAG speed, then use
SAMPLE instruction.  Or, am I way off base here?  Would it get too messy
and should I just provite the read-back path at the cost of higher
pincount?

Thank you in advance for any input/suggestion.

To reply via email, change 'hard' to 'easy'.

> The SRAM I'm thinking of using is Cypress,
will be running it at
> 150+Mhz, and the device supports these JTAG instructions : EXTEST,
> IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported,
> actually).

Are the SRAM read control signals connected to the FPGA? If not, I think you
will need to use INTEST instruction, but looks like the SRAM does not
support it.

Jim Wu
j...@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

Thanks for your response.

The read control is/can be attached to the SRAM from the FPGA, but
do I need to run the read state machine to match the JTAG interface
speed(10Mhz?)

Is this going to turn into a project of its own?  (Don't I need to
somehow synchronize hw and sw - use hw to initiate read at a slower
speed, then check with SAMPLE instruction via sw, back to hw to
increment addr, etc.?)

Thanks again.

(replace 'hard' with 'easy' in email)

"Jim Wu" <j...@yahoo.com> wrote in message
news:<%H3tb.20749$h...@nwrdny02.gnilink.net>...
> > The SRAM I'm thinking of using is Cypress, will be running it at
> > 150+Mhz, and the device supports these JTAG instructions : EXTEST,
> > IDCODE, SAMPLE Z, SAMPLE/PRELOAD, BYPASS (Preload isn't supported,
> > actually).
> 
> Are the SRAM read control signals connected to the FPGA? If not, I think you
> will need to use INTEST instruction, but looks like the SRAM does not
> support it.
> 
> Jim Wu
> j...@yahoo.com (remove capital letters)
> http://www.geocities.com/jimwu88/chips

> Is this going to turn into a project of its
own?  (Don't I need to
> somehow synchronize hw and sw - use hw to initiate read at a slower
> speed, then check with SAMPLE instruction via sw, back to hw to
> increment addr, etc.?)

You can also do it purely using JTAG with a combination of EXTEST and SAMPLE
commands. Use EXTEST to set up read controls and address via FPGA pins and
then use SAMPLE to read the SRAM data back.


Jim Wu
j...@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips