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Hi, I am working on a 10 Gb Ethernet project (deep packet inspection) and needto implement CAM in my FPGA. I am using a Stratix GX and I don't think Ican use CAM (internal or external) in the stratix GX Dev Board. Let me know your thoughts about that. Thanks a lot.______________________________
Freechip, http://www.xilinx.com/products/design_resources/mem_corner/grouping/cam.htm I am not suggesting you switch to Xilinx, but we do have answers. Austin freechip wrote: > Hi, > I am working on a 10 Gb Ethernet project (deep packet inspection) and need > to implement CAM in my FPGA. I am using a Stratix GX and I don't think I > can use CAM (internal or external) in the stratix GX Dev Board. > > Let me know your thoughts about that. > > Thanks a lot.
"freechip" <f...@hotmail.fr> wrote in message news:V...@giganews.com... > > Hi, > I am working on a 10 Gb Ethernet project (deep packet inspection) and need > to implement CAM in my FPGA. I am using a Stratix GX and I don't think I > can use CAM (internal or external) in the stratix GX Dev Board. > > Let me know your thoughts about that. > > Thanks a lot. How big a (Ternary?)CAM do you need?
>"freechip" <f...@hotmail.fr> wrote in message >news:V...@giganews.com... >> >> Hi, >> I am working on a 10 Gb Ethernet project (deep packet inspection) andneed >> to implement CAM in my FPGA. I am using a Stratix GX and I don't thinkI >> can use CAM (internal or external) in the stratix GX Dev Board. >> >> Let me know your thoughts about that. >> >> Thanks a lot. > >How big a (Ternary?)CAM do you need? > > Hi, I don't yet. Do you think it is possible with Altera products? Have a good day.
Hi freechip, yes I think it is possible to build a CAM around Altera RAM blocks. How big is the CAM ? After how many clock cycles do you need a hit ? Rgds Andr=E9
>Hi freechip, > >yes I think it is possible to build a CAM >around Altera RAM blocks. > >How big is the CAM ? After how many clock cycles >do you need a hit ? > >Rgds >Andr=E9 > > Hi Andr, Actually, I am in the research phase and I really don't know how big isthe cam. I just wanted to know, to compare to Xilinx Family, if it waspoosible to use cam with Altera product. For my project (deep packetinspection), the use of the cam is necessary. If you can tell me how can a build a cam around Altera RAM block (and themax. of the cam without my answers to your questions), I will be verypleased. Thanks.______________________________
>>How big a (Ternary?)CAM do you need? >> >> freechip wrote: > > Hi, > I don't yet. > Do you think it is possible with Altera products? > Have a good day. It's possible to build teeny, tiny CAMs. The information Austin pointed out gives you an idea of what you can accomplish with FPGA resources that can apply to all FPGAs, not just Xilinx. If you need a few entries, you might be okay. If you need small entries, you may be able to do many more. Read that documentation and you'll get a feel for the limits you're faced with. Personally, I'd love a 4kx20 CAM but I know there's no way to do it in an FPGA>______________________________
John_H wrote: > It's possible to build teeny, tiny CAMs. The information Austin pointed > out gives you an idea of what you can accomplish with FPGA resources > that can apply to all FPGAs, not just Xilinx. > > If you need a few entries, you might be okay. If you need small > entries, you may be able to do many more. However, if you plan decode 32 bit or 128 bit IP addresses, an FPGA solution will likely cost just as much and not work quite as well as a real CAM. -- Mike Treseler______________________________
"Mike Treseler" <m...@comcast.net> wrote in message news:4...@individual.net... > > However, if you plan decode 32 bit or 128 bit IP addresses, > an FPGA solution will likely cost just as much and not > work quite as well as a real CAM. > > -- Mike Treseler But if each 128-bit IP address only needs 4 slices and the number of IP addresses is rather limited, the cost can be much better than a real CAM.______________________________