Hi,
I am using a DCM in VirtexII which takes a 20 Mhz input and generates a

60 Mhz output.
I am synthesizing using Synplify Pro and using Xilinx ISE 7.1 for PAR.
After PAR, I am getting a warning that the CLKO output from the DCM is
less than 24 MHz. I know that the min. output freq. from the DCM should

be 24 Mhz. In my case, I am getting a 60 MHz output from the CLKFX pin
of the DCM and I am not using the CLKO pin. So, I would like to know
whether this warning will create some problem in the timing of the
clocks in the design. 

Thanks & Regards, 
Srini.

Just ignore the warning. You cannot use CLK0, but
you are using CLKFX,
and you specified multiply by 3 and divide by 1.
Sometimes these warnings are over-eager...
Peter Alfke

Also,

Be sure you are not using CLK90, 180, 270 CLK2X nor CLK2X_b and CLKDV.

Basically if you use any of the DLL outputs, this restriction does 
apply.  Another easy way to tell is if you are not connecting CLKFB, you 
are OK.  If you have connected CLKFB, then the device wants to use the 
DLL as well as the DFS, and the restriction is back again.

Austin



Peter Alfke wrote:

> Just ignore the warning. You cannot use CLK0, but you are using CLKFX,
> and you specified multiply by 3 and divide by 1.
> Sometimes these warnings are over-eager...
> Peter Alfke
>