Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

DCM - Fizzy - 2006-05-17 14:33:00

Does any buddy know How DCM work and does it
require an input clock
sigal or a output signal from external oscillator can work also. Plus
how do i connect my code to the output of DCM

Thanks

______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.



Re: DCM - Falk Brunner - 2006-05-17 14:51:00

Fizzy schrieb:
> Does any buddy know How DCM work and does it require an input clock
> sigal or a output signal from external oscillator can work also. Plus

RTFM.

> how do i connect my code to the output of DCM

Instanciate a component from Coregenerator?

Regards
Falk

Re: DCM - John_H - 2006-05-17 15:05:00

"Fizzy" <f...@gmail.com>
wrote in message 
news:1...@38g2000cwa.googlegroups.com...
> Does any buddy know How DCM work and does it require an input clock
> sigal or a output signal from external oscillator can work also. Plus
> how do i connect my code to the output of DCM
>
> Thanks

In fewer words than the manual which you should read:
o The Delay Locked Loop is at the center.
o A series of delay elements can provide a delay of an input signal such as 
that from an oscillator up to 20 ns, perhaps more.
o This multi-element delay chain is tapped at the right point so the delayed 
input lines up with where you expect the next input to be at the reference 
point you select.
o The DFS mode (frequency synthesis) taps and muxes this same delay line at 
multiple points to give you the M/D frequency ratio.

The output from the DCM is a signal that often goes through a global clock 
buffer.

Fizzy,
  Are you expecting comp.arch.fpga to be an instructional forum for you?  It 
seems many of your posts are very green to the point that it doesn't look 
like you do basic research on the items you have question about.  If you're 
new to programmable logic, welcome to the world ahead of you.  Please read 
the data sheets, read the user guides, read the textbooks on how to code 
HDL.  It's much more effective when this forum is used to help solve 
problems rather than provide basic instruction which otherwise has multiple 
sources.

Happy coding,
- John_H 


______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.