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Comp.Arch.FPGA | memory

There are 1 messages in this thread.

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memory - bhb - 2003-11-25 12:25:00

Hi,

I'm looking for a VHDL example code to implement a DDR memory in a Altera
'Stratix'.
(not a controler), with use of RAS, CAS, etc...
There is many example of memory in Megawizard of Quartus (DP-RAM, FIFO), but
I can't find DDR.

I would like to have this DDR include in specific memory block (M-RAM or
M512 or others).

Thanks for your help,

bhb