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Comp.Arch.FPGA | register state when power on
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register state when power on - bjzhangwn - 2006-07-01 06:39:00
I want to know the registers state after the configurations(altera)
Re: register state when power on - Rob - 2006-07-03 14:30:00
Oddly enough your answer is given in any of Altera's FPGA data sheets. Below is a sentence pulled from the Stratix data sheet. User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistors on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform the function assigned in the user's design. "bjzhangwn" <b...@126.com> wrote in message news:1...@d56g2000cwd.googlegroups.com... >I want to know the registers state after the configurations(altera) >