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Comp.Arch.FPGA | design in vsprom
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design in vsprom - wuyi316904@gmail.com - 2006-07-03 11:36:00
I have a design for vsprom.My idea is that config FPGA with Xilinx CPLD and parallel flash memory.The design is correct in spartan platform but failure in spartan-2.Can u give me some suggestions? I know that the algorithm of config spartan and sparan-2 is different.There is a internal counter for spartan bitstream,but the spartan-2 use command reg for the bitstream control.Is this the reason why the design does't work for spartan-2?
