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Comp.Arch.FPGA | Simulation problem for the DDR controller

There are 2 messages in this thread.

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Simulation problem for the DDR controller - subint - 2006-07-06 06:17:00

Hi,
  I am using the DDR controller(generated by MIG1.5) for the ddr
MT46V32M16 -6 for the board V4MBlx60. I am getting the expected result
in simulation with the hdl code generated by the MIG.But when i tried
to simulate the post-par model of the code all interfaces to the ddr
are driven with x.Any idea.
thanks in advance
subin



Re: Simulation problem for the DDR controller - subint - 2006-07-07 07:49:00

Helloo,
        Anyone who worked with MIG ddr controller please help me.
subint wrote:
> Hi,
>   I am using the DDR controller(generated by MIG1.5) for the ddr
> MT46V32M16 -6 for the board V4MBlx60. I am getting the expected result
> in simulation with the hdl code generated by the MIG.But when i tried
> to simulate the post-par model of the code all interfaces to the ddr
> are driven with x.Any idea.
> thanks in advance
> subin
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