Hi,
Is it ok not to connect at least one DDR Address signal to a ddr
controller? If so, should i connect it to GND or VCCIO? Thanks.

Might be some trouble if this is an SDRAM with a
control register.
What are you up to?


"yy" <y...@yahoo.com.ph> wrote in message 
news:1...@m7g2000cwm.googlegroups.com...
> Hi,
> Is it ok not to connect at least one DDR Address signal to a ddr
> controller? If so, should i connect it to GND or VCCIO? Thanks.
> 

Ayon kay Brad Smallridge:
> Might be some trouble if this is an SDRAM with a control register.
> What are you up to?
>
>
> "yy" <y...@yahoo.com.ph> wrote in message
> news:1...@m7g2000cwm.googlegroups.com...
> > Hi,
> > Is it ok not to connect at least one DDR Address signal to a ddr
> > controller? If so, should i connect it to GND or VCCIO? Thanks.
> >

Hi Brad,
 My design is out of IO pins, BTW i use an FPGA ddr controller core..

yy wrote:
> Ayon kay Brad Smallridge:
>> Might be some trouble if this is an SDRAM with a control register.
>> What are you up to?
>>
>>
>> "yy" <y...@yahoo.com.ph> wrote in message
>> news:1...@m7g2000cwm.googlegroups.com...
>>> Hi,
>>> Is it ok not to connect at least one DDR Address signal to a ddr
>>> controller? If so, should i connect it to GND or VCCIO? Thanks.
>>>
> 
> Hi Brad,
>  My design is out of IO pins, BTW i use an FPGA ddr controller core..
> 

The main thing you need to be careful of is the initialization phase of 
the DDR (assuming you need initialization). This requires that you be 
able to access certain specific addresses.

yy wrote:
> Ayon kay Brad Smallridge:
> 
>>Might be some trouble if this is an SDRAM with a control register.
>>What are you up to?
>>
>>
>>"yy" <y...@yahoo.com.ph> wrote in message
>>news:1...@m7g2000cwm.googlegroups.com...
>>
>>>Hi,
>>>Is it ok not to connect at least one DDR Address signal to a ddr
>>>controller? If so, should i connect it to GND or VCCIO? Thanks.
>>>
> 
> 
> Hi Brad,
>  My design is out of IO pins, BTW i use an FPGA ddr controller core..
> 

This is such an odd question. The obvious answer is look at
the datasheet on the ddr. ddr needs to be configured. This
is done by putting a special address on the address lines.
Which address bits need to be changing? Which can be
tied to 0 or 1, or another address bit? Every address bit you
remove will knock out at least 50% of the storage capacity of
the ram, and these accumulate. Lose enough bits and the
bits start knocking out 75% of the remainder. You've also
got 2 bank bits -- you can tie them together. Or tie them
to 0, at the expense of losing 50% or 75% of capacity.

So you're out of io pins, but the design isn't finalized. Get a
more io-centric part. This is like a jockey who's worried
about being too heavy, so he's wondering if he cuts off a
hand will he be able to handle the horse?

There just isn't enough information in your question to go on.
Failing that, you've got to do the studying and figure it out
for yourself. I would think it's certainly possible to cut out
pins to the DDR, but at what cost? You've got to figure that
out.

A better approach to reducing pins, ddr related, might be
to let data pins float, or perhaps get an 8 bit part instead of
a 16 bit one. By adding one address bit you can half the
number of data pins without losing memory. Probably you
can tie unused data pins to a pullup or pulldown.


-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Ayon kay David Ashley:
> yy wrote:
> > Ayon kay Brad Smallridge:
> >
> >>Might be some trouble if this is an SDRAM with a control register.
> >>What are you up to?
> >>
> >>
> >>"yy" <y...@yahoo.com.ph> wrote in message
> >>news:1...@m7g2000cwm.googlegroups.com...
> >>
> >>>Hi,
> >>>Is it ok not to connect at least one DDR Address signal to a ddr
> >>>controller? If so, should i connect it to GND or VCCIO? Thanks.
> >>>
> >
> >
> > Hi Brad,
> >  My design is out of IO pins, BTW i use an FPGA ddr controller core..
> >
>
> This is such an odd question. The obvious answer is look at
> the datasheet on the ddr. ddr needs to be configured. This
> is done by putting a special address on the address lines.
> Which address bits need to be changing? Which can be
> tied to 0 or 1, or another address bit? Every address bit you
> remove will knock out at least 50% of the storage capacity of
> the ram, and these accumulate. Lose enough bits and the
> bits start knocking out 75% of the remainder. You've also
> got 2 bank bits -- you can tie them together. Or tie them
> to 0, at the expense of losing 50% or 75% of capacity.
>
> So you're out of io pins, but the design isn't finalized. Get a
> more io-centric part. This is like a jockey who's worried
> about being too heavy, so he's wondering if he cuts off a
> hand will he be able to handle the horse?
>
> There just isn't enough information in your question to go on.
> Failing that, you've got to do the studying and figure it out
> for yourself. I would think it's certainly possible to cut out
> pins to the DDR, but at what cost? You've got to figure that
> out.
>
> A better approach to reducing pins, ddr related, might be
> to let data pins float, or perhaps get an 8 bit part instead of
> a 16 bit one. By adding one address bit you can half the
> number of data pins without losing memory. Probably you
> can tie unused data pins to a pullup or pulldown.
>
>
> --
> David Ashley                http://www.xdr.com/dash
> Embedded linux, device drivers, system architecture

I guess you're right...