Hi, I have a Microblaze based project that
communicates to a 16Bit DAC
by means of an SPI interface.  I'm using the OPB_SPI interface with a
OPB to SPI clock ratio of 16 (the minimum for this property) which
works out to be a clock of 3.125 Mhz for a 50Mhz OPB bus.  This seems
extremely slow considering that the DAC unit can work up to an SPI
clock frequency of 30Mhz.  Does anyone know why the minimum value for
the OPB to SPI clock ratio has to 16 or am I just not configuring it
properly.

Aaron Curtin schrieb:

> Hi, I have a Microblaze based project that communicates to a 16Bit DAC
> by means of an SPI interface.  I'm using the OPB_SPI interface with a
> OPB to SPI clock ratio of 16 (the minimum for this property) which
> works out to be a clock of 3.125 Mhz for a 50Mhz OPB bus.  This seems
> extremely slow considering that the DAC unit can work up to an SPI
> clock frequency of 30Mhz.  Does anyone know why the minimum value for
> the OPB to SPI clock ratio has to 16 or am I just not configuring it
> properly.

min ratio is 2 not 16

Antti

Aaron Curtin wrote:
> Does anyone know why the minimum value for
> the OPB to SPI clock ratio has to 16 or am I just not configuring it
> properly.

The minimum ratio value is 2, at least from OPB SPI version 1.00.b
onward
(I don't have a datasheet for version 1.00.a).

>From the Data Sheet:

OPB to SPI SCK frequencies ratio
C_OPB_SCK_RATIO
2, 4, 16, 32, NX16 for N=1,2,3,...,128
default: 2 
type: integer

I have been using version 1.00.e of the opb_spi
interface.  I tried
changing the value in the opb_spi property window and it always resets
to 16 if the value entered is below.  I then tried changing the value
in the MHS file and I end up getting the following error when I try
building the hardware design:

ERROR:MDT - SPI_DAC (opb_spi) - Invalid parameter:
   C_OPB_SCK_RATIO must be 16N where N = 1, 2, 3,...,128
       while executing
   "error "Invalid parameter:\nC_OPB_SCK_RATIO must be 16N where N = 1,
2,
   3,...,128" "" "mdt_err""
       (procedure "check_sck_ratio" line 10)
       invoked from within
   "check_sck_ratio     $mhsinst"
       (procedure "::hw_opb_spi_v1_00_e::check_iplevel_settings" line
4)
       invoked from within
   "::hw_opb_spi_v1_00_e::check_iplevel_settings 34196856"

Running UPDATE Tcl procedures for OPTION
PLATGEN_SYSLEVEL_UPDATE_PROC...
ERROR:MDT - platgen failed with errors!

Aaron, I think it's bug in the GUI, just edit the
mhs by hand.
Aurash
Aaron Curtin wrote:

>I have been using version 1.00.e of the opb_spi interface.  I tried
>changing the value in the opb_spi property window and it always resets
>to 16 if the value entered is below.  I then tried changing the value
>in the MHS file and I end up getting the following error when I try
>building the hardware design:
>
>ERROR:MDT - SPI_DAC (opb_spi) - Invalid parameter:
>   C_OPB_SCK_RATIO must be 16N where N = 1, 2, 3,...,128
>       while executing
>   "error "Invalid parameter:\nC_OPB_SCK_RATIO must be 16N where N = 1,
>2,
>   3,...,128" "" "mdt_err""
>       (procedure "check_sck_ratio" line 10)
>       invoked from within
>   "check_sck_ratio     $mhsinst"
>       (procedure "::hw_opb_spi_v1_00_e::check_iplevel_settings" line
>4)
>       invoked from within
>   "::hw_opb_spi_v1_00_e::check_iplevel_settings 34196856"
>
>Running UPDATE Tcl procedures for OPTION
>PLATGEN_SYSLEVEL_UPDATE_PROC...
>ERROR:MDT - platgen failed with errors!
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Thank you for the reply... I did change the mhs
file by hand to a value
of 8 for the C_OPB_SCK_RATIO parameter but that is resulting in my
previously posted error message.  Is it possible to use an earlier
version of the interface?

Thanks

Here is a snippet of the final error after
changing the mhs file and
re-implementing the design.

ERROR:MDT - C:\Spartan3E_Projects\PWM_IPIF\system.mhs line 179 -
PARAMETER C_OPB_SCK_RATIO has value 2 which does not fall in the range
(16:2048), specified in MPD

What is the MPD?

Aaron Curtin wrote:
> Here is a snippet of the final error after changing the mhs file and
> re-implementing the design.
>
> ERROR:MDT - C:\Spartan3E_Projects\PWM_IPIF\system.mhs line 179 -
> PARAMETER C_OPB_SCK_RATIO has value 2 which does not fall in the range
> (16:2048), specified in MPD
>
> What is the MPD?

Interesting.
In the 1.00.d core, the range in the MPD is 2 to 2048, in the 1.00.e
core, its 16 to 2048.

The MPD files are under the EDK tree, per core.
Example for my installation:

C:\EDK8.1\hw\XilinxProcessorIPLib\pcores\opb_spi_v1_00_d\data\opb_spi_v2_1_0.mpd

> Interesting.
> In the 1.00.d core, the range in the MPD is 2 to 2048, in the 1.00.e
> core, its 16 to 2048.
>
> The MPD files are under the EDK tree, per core.
> Example for my installation:
>
> C:\EDK8.1\hw\XilinxProcessorIPLib\pcores\opb_spi_v1_00_d\data\opb_spi_v2_1_0.mpd

Try using 1.00.d instead

In the 1.00.e data sheet, there is the following note on page 5:

Notes:
1.Ratios of 2 and 4 are not supported in this release of the core.


I quickly scanned the datasheet, but didn't see any explanation of why
this restriction exists in this newest version of the core.