May I connect 11 PCI cards (in each I use Xilinx
FPGA) in one PCI bus,
if use to generate IDSEL signals AD 12...AD31 lines. One card is master
and other is slave.

axalay schrieb:
> May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus,
> if use to generate IDSEL signals AD 12...AD31 lines. One card is master
> and other is slave.
> 
Hi,

actually I have no PCI spec at hand. However 11 PCI loads seems to be
far more than I have used, even in Compact PCI Setups ...

Cheers

axalay a écrit :
> May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus,
> if use to generate IDSEL signals AD 12...AD31 lines. One card is master
> and other is slave.
> 

Hi
The PCI rule of thumb is "no more than 10 loads on a single bus", a PCI 
connector counting for 1 load (thus a card in a slot counts for 2 loads)
You may need to add PCI-PCI bridges to split your bus.

Nicolas

Not quite 11 buy we have something like 6 way
arrays of our products.
Basically the maximum a standard motherboard we have does.

If you are doing a custom system essentially based on PCI then there is
a good chance that it will work providing either the bus segments on
your motherboard are not too long or you can slow the clock rate down a
little. Propagation time and keeping it down is the key. If these are
your own cards you should have a good idea of your I/O timing and what
margin you have to play with. Otherwise if your are using cards by
outside vendors then there is a possability not meeting timing if they
are relatively slow. There are also lots of things either not covered
very well by the PCI spec or simply things people have chosen to ignore
so be slightly beware. The words compatible and compliant come to mind.

The usual problem comes if your cards want to be bus initator capable
and you need support for the grant and request lines. If you case
sounds like you are just using them as slaves so that should not be an
issue.

John Adair
Enterpoint Ltd.

axalay wrote:
> May I connect 11 PCI cards (in each I use Xilinx FPGA) in one PCI bus,
> if use to generate IDSEL signals AD 12...AD31 lines. One card is master
> and other is slave.