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Comp.Arch.FPGA | drive LVDS clocks with a spartan3

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

drive LVDS clocks with a spartan3 - Julien Lochen - 2006-11-09 04:31:00

Hello,

I work as Design Engineer at Bull SAS in France (Server Design and
Development).

I saw a webcase on the web in which someone try to provide some
guidance concerning LVDS signals. I am not sure to have understood all
your answers, so please let me ask the following question :

I am currently working on a design based on the spartan XC3S1000.

Can it be used to drive LVDS clocks ? (LVDS clock's frenquency is 100
Mhz).

If yes, what output buffers should we use ? (Is there an "OBUFGDS" in
the XC3S1000 ?).

What will be the maximum jitter between these 100Mhz-LVDS clocks ?

Thanks a lot for your answers, Julien



Re: drive LVDS clocks with a spartan3 - John Adair - 2006-11-09 13:02:00

You can use the OBUFDS for differential output.
You should be able to
the same with I/O constraints. You will need to use an bank voltage of
2.5V for output LVDS operation.

There will be a skew between output pairings. If they are clocked
outputs with flip-flops in the I/O then that is related to differences
in internal clock routing delays.If you are just doing a route through
from a clock source there will be variance due to differences in
internal routing delays. There will also be small variance due to bond
out wires/routing.

Jitter will depend on your clock sources. If you use a DCM there will
be jitter related to that. Your origional clock source will have jitter
too and that can be impressed on outputs.

John Adair
Enterpoint Ltd.

Julien Lochen wrote:
> Hello,
>
> I work as Design Engineer at Bull SAS in France (Server Design and
> Development).
>
> I saw a webcase on the web in which someone try to provide some
> guidance concerning LVDS signals. I am not sure to have understood all
> your answers, so please let me ask the following question :
>
> I am currently working on a design based on the spartan XC3S1000.
>
> Can it be used to drive LVDS clocks ? (LVDS clock's frenquency is 100
> Mhz).
>
> If yes, what output buffers should we use ? (Is there an "OBUFGDS" in
> the XC3S1000 ?).
>
> What will be the maximum jitter between these 100Mhz-LVDS clocks ?
> 
> Thanks a lot for your answers, Julien