Hello all,
I just wanted to find out how good system generator software is? I can
program in VHDL and would like to know if the SYS gen software would
make life easier for me when it comes to designing DSP filters , FFTS
or other DSP blocks.
Does Xilinx  provide IPs separately for the DSP blocks? If so then How
different is it from using Xilinx IP in the design instead of sysgen
blocks ?
Any experience on system generator software would be helpful .
Thanks,
nbg

Since nobody wants to answer... I don't have any
practical experience with
sysgen, but here is what I know:

1. It seems that Xilinx uses sysgen internally to develop their new cores.
As a result some of the newer cores are not available through coregen, but
only through sysgen or through a special request for a netlist. For example,
take a look at their DUC core or at the Continuously Variable Fractional
Rate Decimator described in the appnote XAPP936.

2. Sysgen in concert with MATLAB Simulink seems to be a nice tool helping to
visualize what happens with the signal. However I am not at all sure this
tool won't be an annoying extra layer of complexity when designing low level
interfaces between the modules.

3. Sysgen + Simulink cost a lot of money.


/Mikhail


<n...@gmail.com> wrote in message
news:1...@s34g2000cwa.googlegroups.com...
> Hello all,
> I just wanted to find out how good system generator software is? I can
> program in VHDL and would like to know if the SYS gen software would
> make life easier for me when it comes to designing DSP filters , FFTS
> or other DSP blocks.
> Does Xilinx  provide IPs separately for the DSP blocks? If so then How
> different is it from using Xilinx IP in the design instead of sysgen
> blocks ?
> Any experience on system generator software would be helpful .
> Thanks,
> nbg
>

"MM" <m...@yahoo.com> wrote in message 
news:5...@mid.individual.net...

> 1. It seems that Xilinx uses sysgen internally to develop their new cores.

Well... that's not really true. Sure, there are certain pieces of DSP IP 
that are produced using System Generator, mostly as part of application 
notes / reference designs. But the majority of cores (i.e. generic, 
parameterizable, optimized, documented, extensively verified IP blocks) are 
delivered through coregen.

We aim to make IP available in the most convenient form possible. Obviously 
not everyone has or wants the System Generator tool, and therefore we 
continue to provide IP for users who have chosen a standard HDL design flow.

In any case, a block designed in Sysgen can be exported and incorporated 
into a larger design done in HDL, and a block design in HDL can similarly be 
incorporated into a Sysgen design.

Your other two points are valid though (hope I don't get into any trouble 
for saying that! :))

Cheers,

    -Ben- 

Thanks for talking to us Ben!

>> 1. It seems that Xilinx uses sysgen internally to develop their new 
>> cores.
>
> Well... that's not really true. Sure, there are certain pieces of DSP IP 
> that are produced using System Generator, mostly as part of application 
> notes / reference designs. But the majority of cores (i.e. generic, 
> parameterizable, optimized, documented, extensively verified IP blocks) 
> are delivered through coregen.

This is good to hear. Can I ask you then to move the DUC into coregen. It 
would be also very nice if one could choose complex input for the DDC and 
complex output for the DUC, as well as multichannel optimization.

> In any case, a block designed in Sysgen can be exported and incorporated 
> into a larger design done in HDL,

Yes, but one needs to have Sysgen for that...

Thanks,
/Mikhail 

"MM" <m...@yahoo.com> writes:

> Since nobody wants to answer... I don't have any practical experience with
> sysgen, but here is what I know:
>

I wrote of my experience a while ago:
http://groups.google.co.uk/group/comp.lang.vhdl/browse_thread/thread/9413e46f42c3ec64/3b32
04ff45804367?lnk=st&q=martin.j.thompson%40trw.com+sysgen&rnum=3&hl=en#3b3204ff
45804367

I guess there's more blocks in there now, and the integration with
AccellDSP might be of benefit, but we didn;t feel much benefit from it
on the project we were doing.

<snip>

> 3. Sysgen + Simulink cost a lot of money.
>

Sysgen isn't *that* expensive if you are already Matlab/Simulink
inclined.


-- 
m...@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

   

"MM" <m...@yahoo.com> wrote in
message 
news:5...@mid.individual.net...
> Thanks for talking to us Ben!

You are welcome, although I am probably not the most useful person to talk 
to about this particular subject :-)

>> But the majority of cores (i.e. generic, parameterizable, optimized, 
>> documented, extensively verified IP blocks) are delivered through 
>> coregen.
> This is good to hear. Can I ask you then to move the DUC into coregen. It 
> would be also very nice if one could choose complex input for the DDC and 
> complex output for the DUC, as well as multichannel optimization.

I should certainly like these up/down converter blocks available outside of 
the SysGen environment too, although I certainly don't have much say in the 
matter I'm afraid. I'm happy to pass requests on to the right people. If 
there is a certain critical mass of people who want a particular piece of IP 
in a particular format, then obviously we'll do our best to provide that.

>> In any case, a block designed in Sysgen can be exported and incorporated 
>> into a larger design done in HDL,
> Yes, but one needs to have Sysgen for that...

Well, mostly true I suppose. Although if you buy the IP from Xilinx I'm sure 
you would be able to get netlists that would work without System 
Generator...

Cheers,

    -Ben-