Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | DRP of the Virtex 5 PLL

There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

DRP of the Virtex 5 PLL - Sylvain Munaut - 2007-03-02 21:20:00

Hi every one,

I see the Virtex 5 DLL has a DRP port however I can't find the register description to
change it's configuration dynamically. For the virtex 4 that was in the
"configuration guide", but looking at the equivalent guide for the virtex 5 I
see no document describing the PLL DRP registers ...

Does any one has info about this ?


Thanks,

	Sylvain