Hi,

I was wondering how the number 166Mhz for DDR came up? Why not say...
200MHz/250MHz DDR? I am sure there is some thought process behind
that, could someone help me walk through?

Thanks in advance !
-Rohit

On Apr 15, 9:33 pm, rohit20...@yahoo.com wrote:
> Hi,
>
> I was wondering how the number 166Mhz for DDR came up? Why not say...
> 200MHz/250MHz DDR? I am sure there is some thought process behind
> that, could someone help me walk through?
>
> Thanks in advance !
> -Rohit

250MHz DDR:
http://www.heise.de/preisvergleich/a174535.html

200MHz DDR
http://dealnews.com/memory/prices/PC1600-DDR-200-MHz/10/512MB.html

450MHz DDR
http://forums.macrumors.com/showthread.php?p=174710

We use 312.5MHz DDR in one of our projects.

So what the f**k are you talking about?

Kolja Sulimma

<r...@yahoo.com> wrote in message 
news:1...@n59g2000hsh.googlegroups.com...
> Hi,
>
> I was wondering how the number 166Mhz for DDR came up? Why not say...
> 200MHz/250MHz DDR? I am sure there is some thought process behind
> that, could someone help me walk through?
>
> Thanks in advance !
> -Rohit
>
Hi Rohit,
It's because the woman who invented DDR memory had polydactylism. See 
http://en.wikipedia.org/wiki/Polydactyl . This meant she could count up to 
6ns on one hand, so she made the operation frequency 1/6ns = c.166MHz
HTH, Syms.

On Apr 15, 12:33 pm, rohit20...@yahoo.com wrote:
> Hi,
>
> I was wondering how the number 166Mhz for DDR came up? Why not say...
> 200MHz/250MHz DDR? I am sure there is some thought process behind
> that, could someone help me walk through?
>
> Thanks in advance !
> -Rohit

Perhaps this number is how slow one can go, not how fast?  If you're
not meeting timing with your FPGA, the low frequency number could be
important.

DDR does have a minimum frequency...

G.

> So what the f**k are you talking about?
>
> Kolja Sulimma

Pleasant!  Errr. but I dont completely agree.

DDR200 = PC1600 = 100MHz ...

www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf" target=_blank rel="nofollow">http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf

Has a bit more detail which may give the OP some information about why 
166MHz was chosen... just a stepping stone really.

Ben

r...@yahoo.com wrote:
> Hi,
> 
> I was wondering how the number 166Mhz for DDR came up? Why not say...
> 200MHz/250MHz DDR? I am sure there is some thought process behind
> that, could someone help me walk through?
> 
> Thanks in advance !
> -Rohit

Why is PCI 33MHz?

If you look at it from the PC angle, almost all clocks are multiples of 
~33.3MHz and the reason for this is to have integer clock multipliers and 
dividers to simplify PLL and related circuitry design.

PC2700 DDR-DIMMs operate at 166MHz, CPU FSBs of that time operated at 
333/667MHz, PCI operated at 33MHz as always, AGP at 66MHz.

So, the 166MHz figure is simply due to PC computing legacy. Within the next 
two years, after PCIe will have completely replaced PCI and AGP, we will 
see other system clocks shift from multiples of 33/66MHz to multiples of 
125/250MHz... or multiples of 75/150MHz if Intel/AMD decide to reuse the 
SATA reference clock instead.

g...@lycos.com wrote:
> On Apr 15, 12:33 pm, rohit20...@yahoo.com wrote:
>> Hi,
>>
>> I was wondering how the number 166Mhz for DDR came up? Why not say...
>> 200MHz/250MHz DDR? I am sure there is some thought process behind
>> that, could someone help me walk through?
>>
> Perhaps this number is how slow one can go, not how fast?  If you're
> not meeting timing with your FPGA, the low frequency number could be
> important.
> 
> DDR does have a minimum frequency...

The minimum operating frequency for DDR DRAMs comes from the DLL circuitry 
used to capture data. My 166MHz Infineon DRAMs say the minimum operating 
frequency for its DLL is 100MHz.

The maximum operating frequency is determined by how fast the DRAM is able 
to get data into or out of the active row (data) register and other control 
structures with the maximum amount of pipelining enabled. Since the high-K 
process used for DRAMs yields slow logic, latency cycles (intermediate 
registers) pile up really fast on high-speed DRAMs.

On 16 Apr., 17:51, "Benjamin Todd"
<benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote:
> > So what the f**k are you talking about?
>
> > Kolja Sulimma
>
> Pleasant!  Errr. but I dont completely agree.
>
> DDR200 = PC1600 = 100MHz ...

Well, both clock frequency and data rate are measured in Hertz.
The OP did not say which 166MHz number he was talking about so it
could have been both.
AFAICT it could also be the number of alpha decays in the solder
balls.

Kolja

On Apr 16, 11:23 pm, "Daniel S."
<digitalmastrmind_no_s...@hotmail.com> wrote:
> ghel...@lycos.com wrote:
> > On Apr 15, 12:33 pm, rohit20...@yahoo.com wrote:
> >> Hi,
>
> >> I was wondering how the number 166Mhz for DDR came up? Why not say...
> >> 200MHz/250MHz DDR? I am sure there is some thought process behind
> >> that, could someone help me walk through?
>
> > Perhaps this number is how slow one can go, not how fast?  If you're
> > not meeting timing with your FPGA, the low frequency number could be
> > important.
>
> > DDR does have a minimum frequency...
>
> The minimum operating frequency for DDR DRAMs comes from the DLL circuitry
> used to capture data. My 166MHz Infineon DRAMs say the minimum operating
> frequency for its DLL is 100MHz.
>
> The maximum operating frequency is determined by how fast the DRAM is able
> to get data into or out of the active row (data) register and other control
> structures with the maximum amount of pipelining enabled. Since the high-K
> process used for DRAMs yields slow logic, latency cycles (intermediate
> registers) pile up really fast on high-speed DRAMs.

Thanks Ben & Daniel ! I think you answered my curiosity question :)

-Uday

r...@yahoo.com wrote:
>>
>> The maximum operating frequency is determined by how fast the DRAM is able
>> to get data into or out of the active row (data) register and other control
>> structures with the maximum amount of pipelining enabled. Since the high-K
>> process used for DRAMs yields slow logic, latency cycles (intermediate
>> registers) pile up really fast on high-speed DRAMs.
> 
> Thanks Ben & Daniel ! I think you answered my curiosity question :)
> 
> -Uday

If your curiosity wants to see something extreme, download datasheet for 
some DDR and DDR2 devices and compare these timings with the latest 1.6GHz 
Samsung GDDR4 devices... there is a pretty drastic difference in the number 
of latency cycles, particularly CAS.