Hi everyone, I want to design a model with my
Smt338. This is a
Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16
as DDR memory. First of all I need to implement the hardware
architecture, so I use edk 8.1 (or edk 8.2) to create a model with
PowerPC and this DDR memory. In the ucf I map every port, but I have
not any pin to DDR_CLK, that is, the feedback ddr clock.

This is the loc entry: Net fpga_0_GEN_DDR_CLK_FB LOC=;

What can I do?. Perhaps I could use a DCM_module but I don't know how
could I implement it.

Regards

Pablo wrote:
> Hi everyone, I want to design a model with my Smt338. This is a
> Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16
> as DDR memory. First of all I need to implement the hardware
> architecture, so I use edk 8.1 (or edk 8.2) to create a model with
> PowerPC and this DDR memory. In the ucf I map every port, but I have
> not any pin to DDR_CLK, that is, the feedback ddr clock.
> 
> This is the loc entry: Net fpga_0_GEN_DDR_CLK_FB LOC=;
> 
> What can I do?. Perhaps I could use a DCM_module but I don't know how
> could I implement it.

One way is to put the feedback on an unused pin:
    DDR_Clk_fb     : inout std_logic;

To keep the timing independent of PAR layout, drive the pin with a DDR 
register:
    DDR_CLK_FB_e: FDDRRSE
    port map (
       Q   => DDR_Clk_fb_o,
       C0  => CLK90,
       C1  => CLK90n,
       CE  => '1',
       D0  => '1',
       D1  => '0',
       R   => '0',
       S   => '0'
    );

Then instantiate the io buffer:

    ddr_clk_io : IOBUF
    port map (
       I => DDR_Clk_fb_o,
       IO => DDR_Clk_fb,
       O => DDR_Clk_fb_i,
       T => '0'
    );

And so, of course, DDR_Clk_fb_i is the input feedback signal.

On 24 mayo, 21:45, Duane Clark
<junkm...@junkmail.com> wrote:
> Pablo wrote:
> > Hi everyone, I want to design a model with my Smt338. This is a
> > Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16
> > as DDR memory. First of all I need to implement the hardware
> > architecture, so I use edk 8.1 (or edk 8.2) to create a model with
> > PowerPC and this DDR memory. In the ucf I map every port, but I have
> > not any pin to DDR_CLK, that is, the feedback ddr clock.
>
> > This is the loc entry: Net fpga_0_GEN_DDR_CLK_FB LOC=3D;
>
> > What can I do?. Perhaps I could use a DCM_module but I don't know how
> > could I implement it.
>
> One way is to put the feedback on an unused pin:
>     DDR_Clk_fb     : inout std_logic;
>
> To keep the timing independent of PAR layout, drive the pin with a DDR
> register:
>     DDR_CLK_FB_e: FDDRRSE
>     port map (
>        Q   =3D> DDR_Clk_fb_o,
>        C0  =3D> CLK90,
>        C1  =3D> CLK90n,
>        CE  =3D> '1',
>        D0  =3D> '1',
>        D1  =3D> '0',
>        R   =3D> '0',
>        S   =3D> '0'
>     );
>
> Then instantiate the io buffer:
>
>     ddr_clk_io : IOBUF
>     port map (
>        I =3D> DDR_Clk_fb_o,
>        IO =3D> DDR_Clk_fb,
>        O =3D> DDR_Clk_fb_i,
>        T =3D> '0'
>     );
>
> And so, of course, DDR_Clk_fb_i is the input feedback signal.

So the process is the following:

1=BA. I design my powerpc model with a generic memory core. This produce
the CLK_DDR_FEEDBACK pin.
2=BA I don't use this pin and (in ISE) I change the system_stub.vhd like
you have said.

Correct me please.

I am very grateful for your help, and if you could send me some file
in which I could see this change.

Thanks again

Pablo

Pablo wrote:
> 
> So the process is the following:
> 
> 1º. I design my powerpc model with a generic memory core. This produce
> the CLK_DDR_FEEDBACK pin.
> 2º I don't use this pin and (in ISE) I change the system_stub.vhd like
> you have said.

That is the way I do it. I always use top level ISE projects, and embed 
EDK systems in them. I don't know how it would be done in a straight EDK 
top level project.

The clock signal should be going off the FPGA through some PCB traces 
and back onto the FPGA feedback pin. If that pin does not exist on the 
board, the method I showed will at least run it through an output and 
input buffer, so the only part that is missing is the time it takes to 
go through the PCB traces. That should be relatively unimportant, in 
part because that time will be virtually a constant.

On May 28, 9:07 pm, Duane Clark
<junkm...@junkmail.com> wrote:
> Pablo wrote:
>
> > So the process is the following:
>
> > 1=BA. I design my powerpc model with a generic memory core. This produce
> > the CLK_DDR_FEEDBACK pin.
> > 2=BA I don't use this pin and (in ISE) I change the system_stub.vhd like
> > you have said.
>
> That is the way I do it. I always use top level ISE projects, and embed
> EDK systems in them. I don't know how it would be done in a straight EDK
> top level project.
>
> The clock signal should be going off the FPGA through some PCB traces
> and back onto the FPGA feedback pin. If that pin does not exist on the
> board, the method I showed will at least run it through an output and
> input buffer, so the only part that is missing is the time it takes to
> go through the PCB traces. That should be relatively unimportant, in
> part because that time will be virtually a constant.

Could you recommend me some manual/tutorial/book to learn how to use
ISE projects. I am able to embed a EDK system in a ISE, but I only see
the ports components and how these map. I am working on how to edit
the ISE project as you have said. I work with Xilinx 8.2 and I think
that in this version you cannot edit cores and things like you say.

Thanks