Hi everyone,

I tried to figure this one out myself but it turns out not so easy for 
someone with this lack of experience like mine. I'm writing a PC app that 
will issue JTAG commands over paralell port to some unspecific FPGA at the 
moment, running let's say some cipher algorithm. I want to use my app to set 
input levels with JTAG and observe how it changes output signals. In order 
to impose signal levels over JTAG with my application I have to somehow 
"halt" the main FPGA clock if I want to do it in an exact moment and here's 
my question: is the FPGA clock stopped when TAP controller is in some 
specific state, concerning JTAG BSR operations or do I have to do it myself 
(how-to?) ?

Thanx in advance!
Chris 

Let me rephrase the question: assuming that TAP
controller is in some other 
state than TEST_LOGIC/RESET is it right that whole FPGA is now clocked with 
TCK clock instead of system main clock? 

On May 28, 10:26 am, "Silver"
<K.Pisan...@gmail.com> wrote:
> Hi everyone,
>
> I tried to figure this one out myself but it turns out not so easy for
> someone with this lack of experience like mine. I'm writing a PC app that
> will issue JTAG commands over paralell port to some unspecific FPGA at the
> moment, running let's say some cipher algorithm. I want to use my app to set
> input levels with JTAG and observe how it changes output signals. In order
> to impose signal levels over JTAG with my application I have to somehow
> "halt" the main FPGA clock if I want to do it in an exact moment and
here's
> my question: is the FPGA clock stopped when TAP controller is in some
> specific state, concerning JTAG BSR operations or do I have to do it myself

There is no JTAG state that stops the FPGA clock (and since an FPGA
is programmable there is no way for JTAG to know what a clock is)

JTAG was designed to run independently of the operation of the chip.
Some processors use it for in system debug.

Using JTAG boundary scan, you can control any input pin (including
clock) and read any output pin.  This would work in non-realtime (very
limited by how fast you can run JTAG).

If you want to run faster, perhaps you should set up some protocol
between the FPGA and your PC.

Alan Nishioka

On May 29, 2:32 pm, "Silver"
<K.Pisan...@gmail.com> wrote:
> Let me rephrase the question: assuming that TAP controller is in some other
> state than TEST_LOGIC/RESET is it right that whole FPGA is now clocked with
> TCK clock instead of system main clock?

No.  JTAG is designed to be non-intrusive unless you tell it to
intrude.

Alan Nishioka
a...@nishioka.com