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Comp.Arch.FPGA | verilog parser question about `defines
There are 4 messages in this thread.
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verilog parser question about `defines - raphfrk - 2007-07-25 05:10:00
I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use. Is there a way to setup Xilinx ISE so that when processing all verilog files it assumes that a certain `define has been defined ?
Re: verilog parser question about `defines - Evan Lavelle - 2007-07-25 08:38:00
On Wed, 25 Jul 2007 02:10:00 -0700, raphfrk <r...@netscape.net> wrote: >I have a set of verilog files that uses `defines. The same `define is >applied to each file to select which code to use. > >Is there a way to setup Xilinx ISE so that when processing all verilog >files it assumes that a certain `define has been defined ? vlogcomp has a '-d' option: evan 63 > vlogcomp Release - ISE Simulator Vlogcomp I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. ... Usage: vlogcomp {options} ... -d <macro> Define <macro>; The format of the <macro> argument is <name>[=<val>] where <name> is the name of the macro, and <val> is an optional value for the macro Evan
Re: verilog parser question about `defines - Gabor - 2007-07-26 09:41:00
On Jul 25, 8:38 am, Evan Lavelle
<nos...@nospam.com> wrote:
> On Wed, 25 Jul 2007 02:10:00 -0700, raphfrk <raph...@netscape.net>
> wrote:
>
> >I have a set of verilog files that uses `defines. The same `define is
> >applied to each file to select which code to use.
>
> >Is there a way to setup Xilinx ISE so that when processing all verilog
> >files it assumes that a certain `define has been defined ?
>
> vlogcomp has a '-d' option:
>
> evan 63 > vlogcomp
> Release - ISE Simulator Vlogcomp I.31
> Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
> ...
> Usage: vlogcomp {options}
> ...
> -d <macro> Define <macro>; The format of the
<macro>
> argument is <name>[=<val>] where <name>
is
> the name of the macro, and <val> is an
> optional
> value for the macro
>
> Evan
You can also add macros in the GUI under synthesis options
(Advanced) "Verilog Macros". Use the same format for
definitions. Use a vertical bar to separate multiple entries.
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Re: verilog parser question about `defines - raphfrk - 2007-07-31 15:41:00
On Jul 26, 2:41 pm, Gabor <ga...@alacron.com> wrote: > You can also add macros in the GUI under synthesis options > (Advanced) "Verilog Macros". Use the same format for > definitions. Use a vertical bar to separate multiple entries. Thanks