I'm working with a custom verilog core that
accepts a small number of 
parameters, and I'm having a hard time pushing them through XST properly 
under EDK 8.1.

For example, I include the following line in my .mpd file:

PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10, 
MIN_SIZE=2, BUS=SDCR

But XST happily reports:

C_DCR_BASEADDR = 32'b00000000000000000000000001000000

Does anybody know how to ensure that my C_DCR_BASEADDR parameter is not 
initialized to something wider than 10 bits?

On Jul 28, 8:17 pm, Neil Steiner
<neil.stei...@vt.edu> wrote:
> I'm working with a custom verilog core that accepts a small number of
> parameters, and I'm having a hard time pushing them through XST properly
> under EDK 8.1.
>
> For example, I include the following line in my .mpd file:
>
> PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10,
> MIN_SIZE=2, BUS=SDCR
>
> But XST happily reports:
>
> C_DCR_BASEADDR = 32'b00000000000000000000000001000000
>
> Does anybody know how to ensure that my C_DCR_BASEADDR parameter is not
> initialized to something wider than 10 bits?


Did you try

C_DCR_BASEADDR=10'b0001000000

Normally verilog assumes integer (32-bit) type for unspecified
bit-widths.  On the other hand are you sure that this matters?
If you assigned the parameter to a 10-bit vector as in

wire [9:0] addr;
assign addr = C_DCR_BASEADDR;

you'd just get the 10 LSB's of the parameter anyway.

HTH,
Gabor

Gabor wrote:
> On Jul 28, 8:17 pm, Neil Steiner <neil.stei...@vt.edu> wrote:
>> I'm working with a custom verilog core that accepts a small number of
>> parameters, and I'm having a hard time pushing them through XST properly
>> under EDK 8.1.
>>
>> For example, I include the following line in my .mpd file:
>>
>> PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10,
>> MIN_SIZE=2, BUS=SDCR
>>
>> But XST happily reports:
>>
>> C_DCR_BASEADDR = 32'b00000000000000000000000001000000
>>
>> Does anybody know how to ensure that my C_DCR_BASEADDR parameter is not
>> initialized to something wider than 10 bits?
> 
> 
> Did you try
> 
> C_DCR_BASEADDR=10'b0001000000

I tried that just now, but platgen doesn't seem very happy with it. 
More specifically, it doesn't seem to recognize 10'b0001000000 as a number.

> Normally verilog assumes integer (32-bit) type for unspecified
> bit-widths.  On the other hand are you sure that this matters?
> If you assigned the parameter to a 10-bit vector as in
> 
> wire [9:0] addr;
> assign addr = C_DCR_BASEADDR;
> 
> you'd just get the 10 LSB's of the parameter anyway.

The little that I do know is that the hardware was responding as if the 
parameter had been zero.  But based on your comments, I'll go ahead and 
dig just a bit more, because there might possibly be some User 
Cluelessness involved.  ;)