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Comp.Arch.FPGA | Altera-Xilinx interfacing SERDES transcievers problem


There are 4 messages in this thread.

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Altera-Xilinx interfacing SERDES transcievers problem - vasile - 2007-08-02 14:11:00

Hi,
Who could enlighten me with the followings:

I need to interface a SERDES transciever from a VIRTEX5 FPGA with a
STRATIX II IO. Things would be easiest if I'll have a Stratix II GX
instead of Stratix II, but the GX FPGA has no HARDCOPY II structured
Altera ASIC corespondent, so I can't use a GX because of finacial
reasons (and huge ball numbers, improper for this design).

How could I get an equivalent of 3Gbps SERDES transciever (like GX
has) using only high speed differential IO available in STRATIX II?

thank you,
Vasile
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Re: Altera-Xilinx interfacing SERDES transcievers problem - 2007-08-02 18:41:00

Good luck!

I think the fastest LVDS serdes you can do in StratixII (non-GX) is
840 Mbps nominal, and 1Gbps with their ALT_LVDS macro and DPA (dynamic
phase alignment) turned on.

If anyone can get it running faster, I look forward to seeing how.
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Re: Altera-Xilinx interfacing SERDES transcievers problem - dimtsios@ix.netcom.com - 2007-08-03 10:18:00

On Aug 2, 11:11 am, vasile
<picli...@gmail.com> wrote:
> Hi,
> Who could enlighten me with the followings:
>
> I need to interface a SERDES transciever from a VIRTEX5 FPGA with a
> STRATIX II IO. Things would be easiest if I'll have a Stratix II GX
> instead of Stratix II, but the GX FPGA has no HARDCOPY II structured
> Altera ASIC corespondent, so I can't use a GX because of finacial
> reasons (and huge ball numbers, improper for this design).
>
> How could I get an equivalent of 3Gbps SERDES transciever (like GX
> has) using only high speed differential IO available in STRATIX II?
>
> thank you,
> Vasile

If cost and size is a concern and you're not stuck on Altera you might
want to look at Lattice's ECP2M family.  Comes in packages as small as
256 pins, provides 3 Gig SERDES, and is very cost effective.

Thanks,
John Dimtsios

Re: Altera-Xilinx interfacing SERDES transcievers problem - vasile - 2007-08-04 03:25:00

On Aug 2, 3:41 pm, jjohn...@cs.ucf.edu wrote:
> Good luck!
>
> I think the fastest LVDS serdes you can do in StratixII (non-GX) is
> 840 Mbps nominal, and 1Gbps with their ALT_LVDS macro and DPA (dynamic
> phase alignment) turned on.
>
> If anyone can get it running faster, I look forward to seeing how.

I'm stucked on Stratix II and Virtex 5.
Fortunately I can use multiple LVDS from both Stratix and Virtex, so I
guess I can create a pack of 1 Gbps "lanes" which could finally
transfer 3Gbps isn't it ?

thx,
Vasile