Hai all,

Can any one suggest with an example how to run c++ code in modelsim
simulator...I didnt understand the example mentioned in modelsim user
guide..Anyone tried this??

regards,
fazal

On 30 Aug, 10:21, fazulu deen
<fazulu.v...@gmail.com> wrote:
> Hai all,
>
> Can any one suggest with an example how to run c++ code in modelsim
> simulator...I didnt understand the example mentioned in modelsim user
> guide..Anyone tried this??

What didn't you understand about it?

Jon

Jon Beniston wrote:
> On 30 Aug, 10:21, fazulu deen <fazulu.v...@gmail.com> wrote:
> > Hai all,
> >
> > Can any one suggest with an example how to run c++ code in modelsim
> > simulator...I didnt understand the example mentioned in modelsim user
> > guide..Anyone tried this??
>
> What didn't you understand about it?
>
>linking was not clear to me and also in my case while simulating the c++ it will
output a test file that has be red by the verilog code...both c++ and verilog is
independent and c++ should be first before verilog after the file is obtained from the c++
simulator the verilog will start....how this can be achieved

On Aug 30, 6:00 am, fazulu deen
<fazulu.v...@gmail.com> wrote:
> Jon Beniston wrote:
> > On 30 Aug, 10:21, fazulu deen <fazulu.v...@gmail.com> wrote:
> > > Hai all,
>
> > > Can any one suggest with an example how to run c++ code in modelsim
> > > simulator...I didnt understand the example mentioned in modelsim user
> > > guide..Anyone tried this??
>
> > What didn't you understand about it?
>
> >linking was not clear to me and also in my case while simulating the c++ it will
output a test file that has be red by the verilog code...both c++ and verilog is
independent and c++ should be first before verilog after the file is obtained from the c++
simulator the verilog will start....how this can be achieved

Fazulu,

If I understand you want to fire-off a thread in C++ and then invoke
the verilog in msim.  While I am not sure this could be done but I
think for all practical purposes you can model your system so that
your logic design (verilog sim) starts first and then invokes C++
routines that comprise your system environment.  I followed the
commands and guidelines shown in msim's documentation for visual c.
And that worked for me.  What did not work was the cygwin commands
they had listed.

-sanjay

On Aug 30, 9:10 pm, fpgabuilder
<fpgabuilder-gro...@yahoo.com> wrote:
> On Aug 30, 6:00 am, fazulu deen <fazulu.v...@gmail.com> wrote:
>
> > Jon Beniston wrote:
> > > On 30 Aug, 10:21, fazulu deen <fazulu.v...@gmail.com> wrote:
> > > > Hai all,
>
> > > > Can any one suggest with an example how to run c++ code in modelsim
> > > > simulator...I didnt understand the example mentioned in modelsim user
> > > > guide..Anyone tried this??
>
> > > What didn't you understand about it?
>
> > >linking was not clear to me and also in my case while simulating the c++ it
will output a test file that has be red by the verilog code...both c++ and verilog is
independent and c++ should be first before verilog after the file is obtained from the c++
simulator the verilog will start....how this can be achieved
>
> Fazulu,
>
> If I understand you want to fire-off a thread in C++ and then invoke
> the verilog in msim.  While I am not sure this could be done but I
> think for all practical purposes you can model your system so that
> your logic design (verilog sim) starts first and then invokes C++
> routines that comprise your system environment.  I followed the
> commands and guidelines shown in msim's documentation for visual c.
> And that worked for me.  What did not work was the cygwin commands
> they had listed.
>
> -sanjay

Hai sanjay,

Exactly you r correct....but did u heard about qverilog command it is
close to my requirement.....

But still i dont know how to invoke it..

regards,
fazal

On Aug 30, 9:10 am, fpgabuilder
<fpgabuilder-gro...@yahoo.com> wrote:
> On Aug 30, 6:00 am, fazulu deen <fazulu.v...@gmail.com> wrote:
>
> > Jon Beniston wrote:
> > > On 30 Aug, 10:21, fazulu deen <fazulu.v...@gmail.com> wrote:
> > > > Hai all,
>
> > > > Can any one suggest with an example how to run c++ code in modelsim
> > > > simulator...I didnt understand the example mentioned in modelsim us=
er
> > > > guide..Anyone tried this??
>
> > > What didn't you understand about it?
>
> > >linking was not clear to me and also in my case while simulating the c=
++ it will output a test file that has be red by the verilog code...both c+=
+ and verilog is independent and c++ should be first before verilog after t=
he file is obtained from the c++ simulator the verilog will start....how th=
is can be achieved
>
> Fazulu,
>
> If I understand you want to fire-off a thread in C++ and then invoke
> the verilog in msim.  While I am not sure this could be done but I
> think for all practical purposes you can model your system so that
> your logic design (verilog sim) starts first and then invokes C++
> routines that comprise your system environment.  I followed the
> commands and guidelines shown in msim's documentation for visual c.
> And that worked for me.  What did not work was the cygwin commands
> they had listed.
>
> -sanjay

Here is the page from msim's manual - although I doubt if you can
still make the C++ code execute first.  Arguable you can execute the C+
+ code at time 0.  But you still have to call launch vsim first after
which it is going to execute c++ objects from the dll.

qverilog

The qverilog command compiles (vlog), optimizes (vopt), and simulates
(vsim) Verilog and SystemVerilog designs in a single step. It combines
the compile, elaborate, and simulate phases together, as some users
may be accustomed to doing with NC-Sim. This command is provided to
ease these users' transition to QuestaSim.

The qverilog command invokes vlog, vopt, and then vsim. All standard
vlog (and vopt) arguments are supported and are applied directly to
the qverilog command line. All vsim options are supported and are
applied through the qverilog -R argument.

You can directly enter either C or C++ file onto the qverilog command
line. QuestaSim automatically processes them using the SystemVerilog
Direct Programming Interface (DPI). Refer to "DPI and the qverilog
Command" for details. If your design contains DPI export tasks or
functions, it is recommended that you use the vlog/vsim flow.

You can invoke the GUI by specifying the -gui argument through the
qverilog -R argument.

By default, qverilog runs the simulation and quits automatically by
invoking an implicit "run -all; quit -f". However, if you invoke
qverilog with -do, -gui, or -I, qverilog invokes the simulator and
keeps it open until you explicitly quit the tool.

The qverilog command creates a work library named work in the current
directory, if not present already.

The command arguments listed below are only those unique to the
qverilog command. This command also supports all vlog command
arguments.

Syntax

qverilog [[<vlog_and_vopt_options>]] [-ccflags "opts"] [-gui] [-l
<logfile>] <filename>
[-ldflags "opts"] [-R <vsim_options>] [-work <library_name>]

Arguments

    * [<vlog_and_vopt_options>]

All vlog and vopt options are supported. For example, if you are
running qverilog on a SystemVerilog design, you need to add the -sv
argument to the command line.

    * -ccflags "opts"

Specifies all C/C++ compiler options. Options are in quotes. Optional.
For -ccflags and -ldflags, qverilog does not check the validity of the
option(s) you specify. The options are directly passed on to the
compiler and linker, and if they are not valid, an error message is
generated by the compiler/linker.

    * -gui

Simulates the design using the ModelSim GUI.

    * -l <logfile>

Creates a logfile/transcript compatible with vlog's -l logfile
argument. Optional. If omitted, a default transcript called
qverilog.log is created that collects the output from vlog, vopt, and
vsim.

    * <filename>

Specifies the name of the Verilog or C/C++ source code file to
compile. One filename is required. Multiple filenames separated by
spaces may be entered. Wildcards may be used. In the case of C files,
they are automatically processed as DPI code.

    * -ldflags "opts"

Specifies all linker options in quotes. Optional.
For -ccflags and -ldflags, qverilog does not check the validity of the
option(s) you specify. The options are directly passed on to the
compiler and linker, and if they are not valid, an error message is
generated by the compiler/linker.

    * -R <vsim_options>

Specifies valid vsim arguments to be applied to the simulation. All
vlog and vopt arguments must come before -R is specified, as all
arguments specified after -R are interpreted as vsim arguments.

    * -work <library_name>

Specifies a logical name or pathname of a library that is to be mapped
to the logical library work. Optional. By default, the compiled design
units are added to the work library. The specified pathname overrides
the pathname specified for work in the project file.

Examples

    * Compile, optimize, and simulate the specified files. The C/C++
code contained in the d.c file is processed as DPI code, creating a
shared object, and loading it into vsim at runtime. Creates a logfile
named "logfile" and opens the QuestaSim GUI with the simulation loaded
and ready to run.

           qverilog -l logfile a.v b.v c.v d.c -R -gui



Questa SV/AFV Reference Manual, 6.3a

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