Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST


Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | [Nios II] How Can I define the pio inputs as a interrupt?

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

[Nios II] How Can I define the pio inputs as a interrupt? - 2007-09-02 22:36:00

I use the Nios II system to achieve my design. I have define a data
bus from the outside of the FPGA, I use a 8-bits PIO ip to connect the
signal and the FPGA.

I want to achieve the following aim: when the outside signals
changes,  Nios generates  a IRQ to CPU, and I can insert my
instructions.

Please tell me , how can I do it ?
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.



Re: [Nios II] How Can I define the pio inputs as a interrupt? - Mark McDougall - 2007-09-02 22:48:00

h...@gmail.com wrote:

> I want to achieve the following aim: when the outside signals
> changes,  Nios generates  a IRQ to CPU, and I can insert my
> instructions.

Read Chapter 13 of the QUartus II Handbook Volume 5.
(aka n2cpu_nii51007-2.pdf)

Or if that's not quite what you need, create a (trivial) SOPC component
that generates an interrupt when you need to.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>;
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Re: How Can I define the pio inputs as a interrupt? - 2007-09-02 23:10:00

Thank you very much! You give me a lot!
______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.