I have an application where I need to model a
circuit that has two
power rails.

A Vitrex-4 has only one internal power rail, so I was thinking about
disabling the DCM to simulate a power-down.

This would be done by taking the signal that is normally used to
enable power to the rest of the chip, and using it to remove the reset
from the DCM.

I'm not concerned with DCM weirdness during start-up; I have to deal
with similar issues when powering up a section of the chip at a time.

Any comments?  Has anyone actually tried this?

Thanks,
Gary.

Gary,

There is the BUFGMUX, which will allow you to switch from a clock, to 
another.

Set it for asynchronous operation (allows a switch to a dead clock), 
,and then just switch over to a BUFG which has no clock on it (connected 
to a '0' or a '1').

I believe that RESET will also work, but as you say, there will be 
transitions that may occur, and if you just want everything to cease, 
the BUFGMUX may be a better test.

Austin (at RADECS 2007, in Deauville, Fr)

Austin

On Sep 10, 11:27 pm, austin
<aus...@xilinx.com> wrote:
> Gary,
>
> There is the BUFGMUX, which will allow you to switch from a clock, to
> another.
>
> Set it for asynchronous operation (allows a switch to a dead clock),
> ,and then just switch over to a BUFG which has no clock on it (connected
> to a '0' or a '1').
>
> I believe that RESET will also work, but as you say, there will be
> transitions that may occur, and if you just want everything to cease,
> the BUFGMUX may be a better test.
>
> Austin (at RADECS 2007, in Deauville, Fr)
>
> Austin

Thanks.