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Comp.Arch.FPGA | synthesizing vqm with parameters with quartus 7.1sp1

There are 2 messages in this thread.

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synthesizing vqm with parameters with quartus 7.1sp1 - 2007-11-18 05:02:00

Hi,

I have a verilog module in my project, which is instantiated in the
design 3 times, each time with different parameters. I generated 3
different vqm files outside the Quartus project (with Synplify), one
for each instantiation. How can I tell Quartus which vqm file should
be linked to its appropriate block?

With regards,
Hezi



Re: synthesizing vqm with parameters with quartus 7.1sp1 - KJ - 2007-11-18 13:53:00

<h...@gmail.com> wrote in message 
news:7...@c30g2000hsa.googlegroups.com...
> Hi,
>
> I have a verilog module in my project, which is instantiated in the
> design 3 times, each time with different parameters. I generated 3
> different vqm files outside the Quartus project (with Synplify), one
> for each instantiation. How can I tell Quartus which vqm file should
> be linked to its appropriate block?
>

By writing the code that instantiates the blocks

KJ
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