How can i interface the cyclone III with 2.5v
LVDS to 3.3v LVDS adc &
dac ?

Thanks

On Nov 29, 6:46 am, "liqi...@gmail.com"
<liqi...@gmail.com> wrote:
> How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc &
> dac ?
>
> Thanks

IMHO directly. I've connected 3.3V Stratix LVDS to 2.5V StratixII LVDS
in both directions.

"The Cyclone III device meets the ANSI/TIA/EIA-644 standard with the
following exceptions:
=94 The maximum voltage output differential (VOD) is increased to 600
mV. The maximum VOD for ANSI specification is 450 mV.
=94 The input voltage range can be reduced to the range of 1.0 V to 1.6
V, 0.5 V to 1.85 V or 0 V to 1.8 V based on different frequency
ranges.
The ANSI/TIA/EIA-644 specification supports an input voltage range of
0V to 2.4V."

See the Cyclone III Device Datasheet: DC and Switching Characteristics
of  Cyclone III Devices chapter in volume 2 of the Cyclone III Device
Handbook
for the LVDS I/O standard electrical specifications and check your DAC/
ADC specification for final proof.

Digitally yours,
 Michael Tsvetkov

http://www.jpegls.com

l...@gmail.com wrote:
> How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc &
> dac ?
> 
> Thanks

If you set 3.3v to a i/o block and Quartus does not allow you to
assign LVDS on a pin of that block (w/ an error message when fitting)
tell quartus you have 2.5v (despite you will use 3.3v in your board)
It will pass compilation and will work great.
I had that issue on CycloneII driving clocks to ADCs from Analog 
devices, I'll bet will be the same on CyIII.


lc.

>> How can i interface the cyclone III with
2.5v LVDS to 3.3v LVDS adc &
>> dac ?
>
>If you set 3.3v to a i/o block and Quartus does not allow you to
>assign LVDS on a pin of that block (w/ an error message when fitting)
>tell quartus you have 2.5v (despite you will use 3.3v in your board)
>It will pass compilation and will work great.
>I had that issue on CycloneII driving clocks to ADCs from Analog 
>devices, I'll bet will be the same on CyIII.

For LVDS transmission from 3.3V I/O, if all three matching resistors
(at the transmitting end) are 150 ohm then this gives output levels to
the LVDS specification and presents 100 ohm to the line.  The only
disadvantage (compared to 2.5V operation) is an increase in power
dissipation.