Hi,

Could anyone explain why FIFO is difficult to implement in FPGA and
ASIC? and how is FIFO implemented in FPGA and ASIC.

Thanks,
Wei

>Could anyone explain why FIFO is difficult to
implement in FPGA and
>ASIC? and how is FIFO implemented in FPGA and ASIC.

Where did you read that a FIFO is difficult to implement?

"Wei Wang" <c...@gmail.com>
wrote in message 
news:c...@e6g2000prf.googlegroups.com...
> Hi,
>
> Could anyone explain why FIFO is difficult to implement in FPGA and
> ASIC? and how is FIFO implemented in FPGA and ASIC.
>
> Thanks,
> Wei

Wei,

According to WHOIS, you're posting from Advanced RISC Machines Ltd. I bet 
there are several people in your office who can answer that for you.

Perhaps no one in the office will talk to you? Googling fifo+fpga returns 
400k hits. Adding I'm+a+little+teapot to the search gets you down to 7.

HTH., Syms.

p.s. http://catb.org/~esr/faqs/smart-questions.html

p.p.s. http://en.wikipedia.org/wiki/Eternal_September 

Wei Wang wrote:

> Could anyone explain why FIFO is difficult to implement in FPGA and
> ASIC? and how is FIFO implemented in FPGA and ASIC.

With dual port memory, like many FPGAs and ASICs have
it isn't difficult to implement.  It isn't for beginners,
but it isn't that hard, either.

In FPGA they are implemented with dual port memory and
two counters.  Also, logic to compare the counters to
generate the full and empty status lines.

-- glen

On Jan 18, 3:54 pm,
MikeShepherd...@btinternet.com wrote:
> >Could anyone explain why FIFO is difficult to implement in FPGA and
> >ASIC? and how is FIFO implemented in FPGA and ASIC.
>
> Where did you read that a FIFO is difficult to implement?

"FIFO" is a broad term and can be either simple or complicated. For
starters, a synchronous (single clock), small FIFO should be easy to
understand and implement. See, for example:
http://www.asic-world.com/examples/vhdl/syn_fifo.html

FIFOs get more complex than that. They can have different clocks for
read and write, they can be large and require a dual port memory
block, etc.

Start with the simple, advance to the more sophisticated when you
need.

Eli

"glen herrmannsfeldt" <g...@ugcs.caltech.edu> wrote in message 
news:r...@comcast.com...
> Wei Wang wrote:
>
>> Could anyone explain why FIFO is difficult to implement in FPGA and
>> ASIC? and how is FIFO implemented in FPGA and ASIC.
>
> With dual port memory, like many FPGAs and ASICs have
> it isn't difficult to implement.  It isn't for beginners,
> but it isn't that hard, either.
>
> In FPGA they are implemented with dual port memory and
> two counters.  Also, logic to compare the counters to
> generate the full and empty status lines.
>
> -- glen
>
Hi Glen,
My favourite FPGA FIFO design is described in XAPP291. The counters' storage 
elements are part of the dual port RAM. "Their advantage is in using only 
one clock load."
Cheers, Syms. 

On Fri, 18 Jan 2008 07:09:47 -0800 (PST), Eli
Bendersky
<e...@gmail.com> wrote:

>On Jan 18, 3:54 pm, MikeShepherd...@btinternet.com wrote:
>> >Could anyone explain why FIFO is difficult to implement in FPGA and
>> >ASIC? and how is FIFO implemented in FPGA and ASIC.
>>
>> Where did you read that a FIFO is difficult to implement?
>
>"FIFO" is a broad term and can be either simple or complicated. For
>starters, a synchronous (single clock), small FIFO should be easy to
>understand and implement. See, for example:
>http://www.asic-world.com/examples/vhdl/syn_fifo.html
>
>FIFOs get more complex than that. They can have different clocks for
>read and write, they can be large and require a dual port memory
>block, etc.
>
>Start with the simple, advance to the more sophisticated when you
>need.
>
>Eli

I'm not planning to start at all.  I was asking a question of the
original poster.

> Hi Glen,
> My favourite FPGA FIFO design is described in XAPP291. The counters' storage elements
are part of 
> the dual port RAM. "Their advantage is in using only one clock load."
> Cheers, Syms.


Pah, I'll beat that for elegance and simplicity....


process(clk,rst)
begin
    one_bit_fifo <= '0';
elsif(rising_edge(clk)) then
    if(load_fifo = '1') then
        one_bit_fifo <= one_bit_fifo_input;
    end if;
end if;
end process;

fifo_output <= one_bit_fifo;



:-)

It _is_ Friday afternoon!


Nial 

> FIFOs get more complex than that. They can
have different clocks for
> read and write, they can be large and require a dual port memory
> block, etc.

I reckon the question was about asynchronous FIFOs and possibly more
on the ASIC side, the Full and Empty signals need some care.

On Jan 18, 11:12=A0am,
"jack.harv...@googlemail.com"
<jack.harv...@googlemail.com> wrote:
> > FIFOs get more complex than that. They can have different clocks for
> > read and write, they can be large and require a dual port memory
> > block, etc.
>
> I reckon the question was about asynchronous FIFOs and possibly more
> on the ASIC side, the Full and Empty signals need some care.

Let me throw in my usual tutorial:
If you have a dual-ported RAM, designing a synchronous (single-clock)
FIFO is trivial.
Designing an asynchronous (two independent clocks) FIFO faces the
tricky issue of detecting Full and Empty. That means detecting the
identity of two counters, which is best done with Gray-coded counters
(which in turn makes it difficult to perform arithmetic on them).

The leading edges of Full and Empty are unproblematic, since they are
generated by the "proper" clock (Empty is generated by a read
operation, and only the read side is interested in the Empty signal)
The VERY TRICKY issues are the trailing edges of Full and Empty, since
they are caused by the "wrong" clock, and thus require
synchronization, and face the UGLY issue of metastability. Enough
problems to give you some grey hair...
Peter Alfke