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Comp.Arch.FPGA | How is FIFO implemented in FPGA and ASIC?
There are 17 messages in this thread.
You are currently looking at messages 10 to 17.
Re: How is FIFO implemented in FPGA and ASIC? - Falk Brunner - 2008-01-18 15:33:00
Peter Alfke schrieb: > synchronization, and face the UGLY issue of metastability. Enough > problems to give you some grey hair... So it looks like you designed quite a lot of those nasty FIFOs . . . SCNR Falk
Re: How is FIFO implemented in FPGA and ASIC? - Peter Alfke - 2008-01-18 16:59:00
On Jan 18, 12:33=A0pm, Falk Brunner <Falk.Brun...@gmx.de> wrote: > Peter Alfke schrieb: > > > synchronization, and face the UGLY issue of metastability. Enough > > problems to give you some grey hair... > > So it looks like you designed quite a lot of those nasty FIFOs . . . > > SCNR > Falk Yes, grey hair, but (still) lots of it ! Today is my 20th anniversary at Xilinx. It has been a very good experience, in every respect... Peter
Re: How is FIFO implemented in FPGA and ASIC? - jack.harvard@googlemail.com - 2008-01-18 17:21:00
On Jan 18, 7:42=A0pm, Peter Alfke <pe...@xilinx.com> wrote: > On Jan 18, 11:12=A0am, "jack.harv...@googlemail.com" > > <jack.harv...@googlemail.com> wrote: > > > FIFOs get more complex than that. They can have different clocks for > > > read and write, they can be large and require a dual port memory > > > block, etc. > > > I reckon the question was about asynchronous FIFOs and possibly more > > on the ASIC side, the Full and Empty signals need some care. > > Let me throw in my usual tutorial: > If you have a dual-ported RAM, designing a synchronous (single-clock) > FIFO is trivial. > Designing an asynchronous (two independent clocks) FIFO faces the > tricky issue of detecting Full and Empty. That means detecting the > identity of two counters, which is best done with Gray-coded counters > (which in turn makes it difficult to perform arithmetic on them). > > The leading edges of Full and Empty are unproblematic, since they are > generated by the "proper" clock (Empty is generated by a read > operation, and only the read side is interested in the Empty signal) > The VERY TRICKY issues are the trailing edges of Full and Empty, since > they are caused by the "wrong" clock, and thus require > synchronization, and face the UGLY issue of metastability. Enough > problems to give you some grey hair... > Peter Alfke Asynchronous FIFO implementation is also explained in Steve Kilts' Advanced FPGA Design book, although not in great details.______________________________
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Re: How is FIFO implemented in FPGA and ASIC? - Falk Brunner - 2008-01-18 17:43:00
Peter Alfke schrieb: > Today is my 20th anniversary at Xilinx. Congratulations! Regards Falk______________________________
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Re: How is FIFO implemented in FPGA and ASIC? - 2008-01-18 20:49:00
On Jan 18, 11:42 am, Peter Alfke <pe...@xilinx.com> wrote: > On Jan 18, 11:12 am, "jack.harv...@googlemail.com" > > <jack.harv...@googlemail.com> wrote: > > > FIFOs get more complex than that. They can have different clocks for > > > read and write, they can be large and require a dual port memory > > > block, etc. > > > I reckon the question was about asynchronous FIFOs and possibly more > > on the ASIC side, the Full and Empty signals need some care. > > Let me throw in my usual tutorial: > If you have a dual-ported RAM, designing a synchronous (single-clock) > FIFO is trivial. > Designing an asynchronous (two independent clocks) FIFO faces the > tricky issue of detecting Full and Empty. That means detecting the > identity of two counters, which is best done with Gray-coded counters > (which in turn makes it difficult to perform arithmetic on them). > > The leading edges of Full and Empty are unproblematic, since they are > generated by the "proper" clock (Empty is generated by a read > operation, and only the read side is interested in the Empty signal) > The VERY TRICKY issues are the trailing edges of Full and Empty, since > they are caused by the "wrong" clock, and thus require > synchronization, and face the UGLY issue of metastability. Enough > problems to give you some grey hair... > Peter Alfke Or just use "coregen". The FIFO's generated by it work pretty darn well. ;) G.
Re: How is FIFO implemented in FPGA and ASIC? - Brian Drummond - 2008-01-19 10:22:00
On Fri, 18 Jan 2008 16:22:59 -0000, "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >Pah, I'll beat that for elegance and simplicity.... > > >process(clk,rst) >begin > one_bit_fifo <= '0'; >elsif(rising_edge(clk)) then > if(load_fifo = '1') then > one_bit_fifo <= one_bit_fifo_input; > end if; >end if; >end process; > >fifo_output <= one_bit_fifo; Where are the empty and full flags? - Brian
Re: How is FIFO implemented in FPGA and ASIC? - Hal Murray - 2008-01-20 01:39:00
>Yes, grey hair, but (still) lots of it ! >Today is my 20th anniversary at Xilinx. >It has been a very good experience, in every respect... >Peter It's been very good for us too. Many thanks. -- These are my opinions, not necessarily my employer's. I hate spam.