Hello all,

I'm evaluating ModelSim versus Active-HDL to determine which one is
better in today's marketplace (for VHDL).  I found some older threads
that seemed to lean towards Active-HDL so I wanted to see if that was
still the case.

I currently use ModelSim Xilinx Edition but my designs often-times hit
XE's limits and get throttled.

Also, does know off-hand the approximate price of the different
versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key
features that make the more expensive ones worth the cost?

Thanks,
John

On Feb 11, 11:29 am, paragon.j...@gmail.com
wrote:
> Hello all,
>
> I'm evaluating ModelSim versus Active-HDL to determine which one is
> better in today's marketplace (for VHDL).  I found some older threads
> that seemed to lean towards Active-HDL so I wanted to see if that was
> still the case.
>
> I currently use ModelSim Xilinx Edition but my designs often-times hit
> XE's limits and get throttled.
>
> Also, does know off-hand the approximate price of the different
> versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key
> features that make the more expensive ones worth the cost?
>
> Thanks,
> John

I use ActiveHDL , It was the first program I learned to use and I am
not changing it for nothing , though I tried ModelSim.
Alfredo

p...@gmail.com wrote:
> Hello all,
> 
> I'm evaluating ModelSim versus Active-HDL to determine which one is
> better in today's marketplace (for VHDL).  I found some older threads
> that seemed to lean towards Active-HDL so I wanted to see if that was
> still the case.
> 
> I currently use ModelSim Xilinx Edition but my designs often-times hit
> XE's limits and get throttled.
> 
> Also, does know off-hand the approximate price of the different
> versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key
> features that make the more expensive ones worth the cost?

There is a big difference between Modelsim PE and SE, including a price 
difference of something like $12K (the last time I looked, which was 
awhile ago). Also, another thing to consider is Aldec Riviera, rather 
than ActiveHDL. This is just a high performance simulator, without all 
the whole "design environment" that ActiveHDL includes.

Also, while you only mention VHDL, keep in mind that you are likely to 
want to be able to do mixed language simulations. For example, a lot of 
good memory models seem to only come in Verilog.

I didn't work with ActiveHDL, but I know that
with ActiveHDL you
cannot do post place and route simulation. This soft is only for
behavioral simulation.

>I didn't work with ActiveHDL, but I know that
with ActiveHDL you
>cannot do post place and route simulation. This soft is only for
>behavioral simulation.
>
Is that because it cannot read SDF files?

nezhate wrote:
> I didn't work with ActiveHDL, but I know that with ActiveHDL you
> cannot do post place and route simulation. This soft is only for
> behavioral simulation.

Well, I will have to admit that it has been several years since I have 
done post place and route simulation. I really don't see much need for 
that in FPGA design.

On Feb 13, 8:30=A0am, Duane Clark
<junkm...@junkmail.com> wrote:

>
> Well, I will have to admit that it has been several years since I have
> done post place and route simulation. I really don't see much need for
> that in FPGA design.



ooo now thats a little scary

Bobsterthelobster

On 11 Feb., 15:29, paragon.j...@gmail.com wrote:
> Also, does know off-hand the approximate price of the different
> versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any

Prices is difficult, as e.g. PE is not like PE, you can buy different
licenses for PE (VHDL vs Verilog, Floating vs Dongle, ...) and you
might get deals when buying more than one SW from same vendor.

> key
> features that make the more expensive ones worth the cost?

For the full range of differences have a look at the Mentor homepage.

For me important:
- Performance optimisations is SE only, Performance reduction should
be designer only.
- SE has a lot of features included, that need additional payment for
the other simulators
- OS support (PE: Win, SE: win, Solaris, Linux (32 and 64 bit), LE:
Linux32 only)
- Tcl/Tk support is SE

bye Thomas

nezhate wrote:

> I didn't work with ActiveHDL, but I know that with ActiveHDL you
> cannot do post place and route simulation. This soft is only for
> behavioral simulation.


I don't know where you got that idea.  Active HDL simulates a post route 
netlist just fine.  Perhaps you didn't have the simprims library?

Active HDL can also simulate an edif netlist, and can co-simulate with 
Matlab as a testbench (something I don't think Modelsim does).

I have both, but I use Active HDL for my day to day work.  I use 
Modelsim pretty much only when I don't have a choice.

b...@yahoo.co.nz wrote:

> On Feb 13, 8:30 am, Duane Clark <junkm...@junkmail.com> wrote:
> 
> 
>>Well, I will have to admit that it has been several years since I have
>>done post place and route simulation. I really don't see much need for
>>that in FPGA design.
> 
> 
> 
> 
> ooo now thats a little scary
> 

Why?  I don't use post PAR simulation unless I have a reason to believe 
the tools messed something up.  I can count on my fingers the number of 
times I've resorted to post PAR simulation.  A functional simulation of 
the RTL followed by a solid timing analysis is far more likely to 
uncover any problems in the design than a post PAR simulation is.