I have a project to prototype an ASIC design on
FPGA. What are the
things I should do? Here is some of my concerns:

1) I understand FPGAs usually have 4 look-up table. Should I rewrite
the ASIC combinational logics to be four-inputs logics to improve the
utilization of FPGA?

2) Netting if and case statements over three layers might results a
poor synthesis result in FPGA . Should I changes those netting codes
in ASIC RTL?

3) ASIC synthesis need to generate clock tree and power rails. In FPGA
synthesis, Maybe I not need to care too much about it?

4) Is there a to-do-list for this kind of job?

Thank you for any advices.

On 20 Feb., 18:00, jasonL
<junsong.l...@gmail.com> wrote:
> I have a project to prototype an ASIC design on FPGA. What are the
> things I should do? Here is some of my concerns:
>
> 1) I understand FPGAs usually have 4 look-up table. Should I rewrite
> the ASIC combinational logics to be four-inputs logics to improve the
> utilization of FPGA?
>
> 2) Netting if and case statements over three layers might results a
> poor synthesis result in FPGA . Should I changes those netting codes
> in ASIC RTL?
>
> 3) ASIC synthesis need to generate clock tree and power rails. In FPGA
> synthesis, Maybe I not need to care too much about it?
>
> 4) Is there a to-do-list for this kind of job?
>
> Thank you for any advices.

1) no, unless you are given the opportunity to get old doing this
project
2) see 1
3) yes
4) Yes, your 1st and only point: give it to a third party

It seems somebody gave you the wrong job, because you neither have
experience with fpga nor asic design. At least basic experience with
FPGA would be needed.

ASIC protoyping using FPGAs is a common enough
occurance. There are multiple 
low priced tool vendors that specialize in this area.  It is best not to 
re-invent the wheel.  Rather look up the tool vendors and let thier tools 
handle the FPGA mapping issues.

The following paper can give you more insight into the process. I doubt you 
will find any FPGA protoype vendors in this paper, Since Mentor has a cycle 
based emulator that they compete against the fpgra protoypes with.

http://www.mentor.com/products/fpga_pld/techpubs/mentorpaper_33693.cfm





"jasonL" <j...@gmail.com> wrote in message 
news:2...@s12g2000prg.googlegroups.com...
>I have a project to prototype an ASIC design on FPGA. What are the
> things I should do? Here is some of my concerns:
>
> 1) I understand FPGAs usually have 4 look-up table. Should I rewrite
> the ASIC combinational logics to be four-inputs logics to improve the
> utilization of FPGA?
>
> 2) Netting if and case statements over three layers might results a
> poor synthesis result in FPGA . Should I changes those netting codes
> in ASIC RTL?
>
> 3) ASIC synthesis need to generate clock tree and power rails. In FPGA
> synthesis, Maybe I not need to care too much about it?
>
> 4) Is there a to-do-list for this kind of job?
>
> Thank you for any advices. 

jasonL schrieb:

> I have a project to prototype an ASIC design on FPGA. What are the
> things I should do? Here is some of my concerns:

Well .. good HDL code should be portable. ;-)


> 1) I understand FPGAs usually have 4 look-up table. Should I rewrite
> the ASIC combinational logics to be four-inputs logics to improve the
> utilization of FPGA?

No. Usually the FPGA is big enough. This is an advanced topic for
highly-optimized designs.


> 2) Netting if and case statements over three layers might results a
> poor synthesis result in FPGA . Should I changes those netting codes
> in ASIC RTL?

Flipflops are free in FPGAs. Therefore you can pipeline your design
easily. The only disadvantage are the additional clocks through the
pipeline.


> 3) ASIC synthesis need to generate clock tree and power rails. In FPGA
> synthesis, Maybe I not need to care too much about it?

Ususally you should place an instance of a component, that tells the
synthesis tool to use global clocks and global signals for reset. For
Xilinx this it a BUFG.


> 4) Is there a to-do-list for this kind of job?

Usually I replace memories with BlockRAM inside the FPGA and use
instances of clock buffers. Thats it.

Fully synchronous designs are easily done on FPGAs, but even highly
clock-gated designs using a lot of latches run quite fine.

Ralf

On Feb 20, 3:45 pm, Ralf Hildebrandt
<Ralf-Hildebra...@gmx.de> wrote:
> jasonL schrieb:
>
> > I have a project to prototype an ASIC design on FPGA. What are the
> > things I should do? Here is some of my concerns:
>
> Well .. good HDL code should be portable. ;-)
>
> > 1) I understand FPGAs usually have 4 look-up table. Should I rewrite
> > the ASIC combinational logics to be four-inputs logics to improve the
> > utilization of FPGA?
>
> No. Usually the FPGA is big enough. This is an advanced topic for
> highly-optimized designs.
>
> > 2) Netting if and case statements over three layers might results a
> > poor synthesis result in FPGA . Should I changes those netting codes
> > in ASIC RTL?
>
> Flipflops are free in FPGAs. Therefore you can pipeline your design
> easily. The only disadvantage are the additional clocks through the
> pipeline.
>
> > 3) ASIC synthesis need to generate clock tree and power rails. In FPGA
> > synthesis, Maybe I not need to care too much about it?
>
> Ususally you should place an instance of a component, that tells the
> synthesis tool to use global clocks and global signals for reset. For
> Xilinx this it a BUFG.
>
> > 4) Is there a to-do-list for this kind of job?
>
> Usually I replace memories with BlockRAM inside the FPGA and use
> instances of clock buffers. Thats it.
>
> Fully synchronous designs are easily done on FPGAs, but even highly
> clock-gated designs using a lot of latches run quite fine.
>
> Ralf

Thank you all for the helps. It seems that a good synthesizer will do
a lot of help.