Hi All

This application I am  looking at requires 17 tera bytes of
multiplication per second. Which in an FPGA  means 40K FPGAs. What I
want to know is how many 32x32 Mults can you fit into an ASIC today
Standard Cell or Custom ASIC. Also what kind of speeds can I  get.


Bye

vipul

"VIPS" <t...@gmail.com> wrote in message
news:3...@k13g2000hse.googlegroups.com...
> Hi All
>
> This application I am  looking at requires 17 tera bytes of
> multiplication per second. Which in an FPGA  means 40K FPGAs. What I
> want to know is how many 32x32 Mults can you fit into an ASIC today
> Standard Cell or Custom ASIC. Also what kind of speeds can I  get.
>

Assuming that you mean 17 10^12 multipliers?

With a 90nm process you can get quite a few in a standard cell ASIC. But
without further explanation, I would say that speed per multiplier will be
dreadfull: you won't be able to get that much data on and off a single chip
(I/O limitations). So you may stick to an FPGA as well (saves you time and
risk, read on).

As for your FPGA count: you need 3 DSP48 blocks on a Xilinx device or 1
32x32 multiplier on an Altera device. The DSP48s go up to 550MHz, for the
Altera part, I don't know.

But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there are
more than 100 of these in the larger V5 SX(T) devices (too lasy to look up
the exact number), you will end up with quite a bit less than 1000 FPGAs.

Still, you need to look at your I/O, power, algorithm, costs, etc. to get
the whole picture.

Regards,
Alvin.

Alvin Andries wrote:
> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there are
> more than 100 of these in the larger V5 SX(T) devices (too lasy to look up
> the exact number), you will end up with quite a bit less than 1000 FPGAs.

Approx 1000 in the SX240, so approx 100 FPGAs. A big project!

"Tim (one of many)" <t...@nooospam.roockyloogic.com> wrote in message 
news:ftghqh$31k$1$8...@news.demon.co.uk...
> Alvin Andries wrote:
>> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there 
>> are
>> more than 100 of these in the larger V5 SX(T) devices (too lasy to look 
>> up
>> the exact number), you will end up with quite a bit less than 1000 FPGAs.
>
> Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
>
Perhaps use the money it costs for all those FPGAs to pay off someone who 
already knows the encryption key?
Just a thought, Syms. 

Tim (one of many) wrote:

> Alvin Andries wrote:
> 
>> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since 
>> there are
>> more than 100 of these in the larger V5 SX(T) devices (too lasy to 
>> look up
>> the exact number), you will end up with quite a bit less than 1000 FPGAs.
> 
> 
> Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
> 

But not totally outrageous.  I've recently completed a beamforming 
antenna design for installation in an aircraft that uses one Virtex 
4SX55 for each antenna element.  There are 240 antenna elements, thus 
240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the 
FPGA is a 10 channel tuner, downconverter, and beam steering.

Ray Andraka <r...@andraka.com> wrote:
> Tim (one of many) wrote:

> > Alvin Andries wrote:
> > 
> >> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since 
> >> there are
> >> more than 100 of these in the larger V5 SX(T) devices (too lasy to 
> >> look up
> >> the exact number), you will end up with quite a bit less than 1000 FPGAs.
> > 
> > 
> > Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
> > 

> But not totally outrageous.  I've recently completed a beamforming 
> antenna design for installation in an aircraft that uses one Virtex 
> 4SX55 for each antenna element.  There are 240 antenna elements, thus 
> 240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the 
> FPGA is a 10 channel tuner, downconverter, and beam steering.

Aren't you supposed to shoot everybody you tell about the project?
-- 
Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Apr 8, 3:11=A0pm, Uwe Bonnes
<b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> Ray Andraka <r...@andraka.com> wrote:
> > Tim (one of many) wrote:
> > > Alvin Andries wrote:
>
> > >> But: 3 * (17 10^12 / 550 10^6) =3D +/- 92800 DSP48 resources. Since
> > >> there are
> > >> more than 100 of these in the larger V5 SX(T) devices (too lasy to
> > >> look up
> > >> the exact number), you will end up with quite a bit less than 1000 FP=
GAs.
>
> > > Approx 1000 in the SX240, so approx 100 FPGAs. A big project!
>
> > But not totally outrageous. =A0I've recently completed a beamforming
> > antenna design for installation in an aircraft that uses one Virtex
> > 4SX55 for each antenna element. =A0There are 240 antenna elements, thus
> > 240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the
> > FPGA is a 10 channel tuner, downconverter, and beam steering.
>
> Aren't you supposed to shoot everybody you tell about the project?
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-darm=
stadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Slightly off-topic: Here is a civilian research application at CERN,
where 120 Virtex 4FX devices "digest" and pre-process a thousand data
streams of 2.5 Gbps each.
I was peripherally involved, and I helped write the press release...
http://biz.yahoo.com/prnews/080404/aqf063.html?.v=3D35
I even got to walk around in the tunnel.
Peter Alfke, Xilinx

Uwe Bonnes wrote:
> Ray Andraka <r...@andraka.com> wrote:
>>But not totally outrageous.  I've recently completed a beamforming 
>>antenna design for installation in an aircraft that uses one Virtex 
>>4SX55 for each antenna element.  There are 240 antenna elements, thus 
>>240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the 
>>FPGA is a 10 channel tuner, downconverter, and beam steering.
> 
> 
> Aren't you supposed to shoot everybody you tell about the project?

Why ? I'm sure this is for a crop-duster, right ? ;)

-jg

VIPS wrote:
> Hi All
> 
> This application I am  looking at requires 17 tera bytes of
> multiplication per second. Which in an FPGA  means 40K FPGAs. What I
> want to know is how many 32x32 Mults can you fit into an ASIC today
> Standard Cell or Custom ASIC. Also what kind of speeds can I  get.

You could also do the calculations for : http://www.mathstar.com/
and once you have the Multiplier count, the data bandwidth to
keep all these fed will be important as well.

-jg

On 9 Apr., 00:58, Peter Alfke
<pe...@xilinx.com> wrote:

> Slightly off-topic: Here is a civilian research application at CERN,
> where 120 Virtex 4FX devices "digest" and pre-process a thousand data
> streams of 2.5 Gbps each.
> I was peripherally involved, and I helped write the press
release...http://biz.yahoo.com/prnews/080404/aqf063.html?.v=35
> I even got to walk around in the tunnel.
> Peter Alfke, Xilinx

So that's why Volker Lindenstruth is hosting the FPL this year.
I worked on something like the predecessor of that beast in 1995.
Processing 100.000 data streams at 10MHz.

Kolja Sulimma