hi,
i have got xilinx fft IP core from coregen. Is there any way that i
can get asic gate count for this ? Any help / hint is greatly
appreciated.

thanks,
vijayant.

v...@gmail.com wrote:

> i have got xilinx fft IP core from coregen. Is there any way that i
> can get asic gate count for this ? Any help / hint is greatly
> appreciated.

An accurate count requires source code.

       -- Mike Treseler

On Apr 15, 1:23 pm,
"vijayant.rutg...@gmail.com"
<vijayant.rutg...@gmail.com> wrote:
> hi,
> i have got xilinx fft IP core from coregen. Is there any way that i
> can get asic gate count for this ? Any help / hint is greatly
> appreciated.
>
> thanks,
> vijayant.

You aren't going to get a corgen part into an ASIC.  Just ain't gonna
happen.

If you build the core into a Xilinx part, then multiply the "marketing
size" of the FPGA by the percentage used, you'll get a number that
will give you an idea of the order of magnitude of an ASIC solution.

G.

On Wed, 16 Apr 2008 10:25:36 -0700 (PDT),
g...@lycos.com wrote:

>On Apr 15, 1:23 pm, "vijayant.rutg...@gmail.com"
><vijayant.rutg...@gmail.com> wrote:
>> hi,
>> i have got xilinx fft IP core from coregen. Is there any way that i
>> can get asic gate count for this ? Any help / hint is greatly
>> appreciated.
>>
>> thanks,
>> vijayant.
>
>You aren't going to get a corgen part into an ASIC.  Just ain't gonna
>happen.

Not necessarily true. It is sometimes possible to buy the RTL from
Xilinx for the coregen part in question. If not, one can always pay
someone (ahem :-) to develop another module which duplicates the
behavior.

Hi,
Is there any software/website that you guyz know that can give me
rough estimate ? I tried chip estimate but it doesnt have gate counts
for IPs like FIR filter. It has got a bunch of IPs without gate count
estimation.

Any help is greatly appreciated.

Thanks,
Vijayant Bhatnagar

On Apr 16, 9:28=A0pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Wed, 16 Apr 2008 10:25:36 -0700 (PDT), ghel...@lycos.com wrote:
> >On Apr 15, 1:23 pm, "vijayant.rutg...@gmail.com"
> ><vijayant.rutg...@gmail.com> wrote:
> >> hi,
> >> i have got xilinx fft IP core from coregen. Is there any way that i
> >> can get asic gate count for this ? Any help / hint is greatly
> >> appreciated.
>
> >> thanks,
> >> vijayant.
>
> >You aren't going to get a corgen part into an ASIC. =A0Just ain't gonna
> >happen.
>
> Not necessarily true. It is sometimes possible to buy the RTL from
> Xilinx for the coregen part in question. If not, one can always pay
> someone (ahem :-) to develop another module which duplicates the
> behavior.

Vijayant wrote:

> Is there any software/website that you guyz know that can give me
> rough estimate ? I tried chip estimate but it doesnt have gate counts
> for IPs like FIR filter. 

Maybe that's because a FIR filter could use
500 gates or 500K gates.

Until you have a rough design,
you can use this estimate:

91 Wed Apr 30 /evtfs/home/tres> python
Python 2.4.2 (#1, Jan 10 2008, 17:45:02)
|>>> from random import *
|>>> randint(1e3, 1e6)
376575

    -- Mike Treseler

Ok. I have my design finalized. The fir length
would be 64 operating
on 32 bit wide word. Now could you please hint me on estimating gate
count ?

Help appreciated,
Vijayant.


On May 1, 2:30=A0am, Mike Treseler <mike_trese...@comcast.net> wrote:
> Vijayantwrote:
> > Is there any software/website that you guyz know that can give me
> > rough estimate ? I tried chip estimate but it doesnt have gate counts
> > for IPs like FIR filter.
>
> Maybe that's because a FIR filter could use
> 500 gates or 500K gates.
>
> Until you have a rough design,
> you can use this estimate:
>
> 91 Wed Apr 30 /evtfs/home/tres> python
> Python 2.4.2 (#1, Jan 10 2008, 17:45:02)
> |>>> from random import *
> |>>> randint(1e3, 1e6)
> 376575
>
> =A0 =A0 -- Mike Treseler

On 1 Mai, 21:54,
"vijayant.rutg...@gmail.com"
<vijayant.rutg...@gmail.com> wrote:
> Ok. I have my design finalized. The fir length would be 64 operating
> on 32 bit wide word. Now could you please hint me on estimating gate
> count ?

Is it serial or parallel? Using RAM or FF? Which ASIC technology?
With tight timing constraints or relaxed timing?

My guess would be 65x32 for storage of input and result and two adders
size 32 bit.

ASIC gate count is a value gained by guess of numbers multiplied with
e^n with n being a marketing factor (technical oriented people assume
n=random(unconstrained) as you can't understand calculation of n if
you'r not member of a marketing department)

bye Thomas

"Back in the day", ASIC gate counts
were mostly estimated by extrapolatingfrom previous ASIC designs. If you don't have any such information, yourguess will be as bad as mine. 

Do as Dilbert does, and just make up the numbers ;-) After all, it's onlythe shareholders' money, and what have they ever done for you?

On May 2, 1:24=A0am, Thomas Stanka
<usenet_nospam_va...@stanka-web.de>
wrote:
> On 1 Mai, 21:54, "vijayant.rutg...@gmail.com"
>
> <vijayant.rutg...@gmail.com> wrote:
> > Ok. I have my design finalized. The fir length would be 64 operating
> > on 32 bit wide word. Now could you please hint me on estimating gate
> > count ?
>
> Is it serial or parallel? Using RAM or FF? Which ASIC technology?
> With tight timing constraints or relaxed timing?
>
> My guess would be 65x32 for storage of input and result and two adders
> size 32 bit.
>
> ASIC gate count is a value gained by guess of numbers multiplied with
> e^n with n being a marketing factor (technical oriented people assume
> n=3Drandom(unconstrained) as you can't understand calculation of n if
> you'r not member of a marketing department)
>
> bye Thomas

it will be parallel implementation using RAM and relaxed timing. Any
help is appreciated.

Thanks,
Vijayant