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Comp.Arch.FPGA | Call VHDL module from Verilog

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

Call VHDL module from Verilog - egadget1 - 2008-05-06 15:38:00

Hi,

 I have a basic question.  Is is possible in the xilinx ISE enviroment
to make a verilog wrapper of some VHDL code.  I don't want to recode
it in verilog.

Thanks
Rob
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Re: Call VHDL module from Verilog - egadget1 - 2008-05-06 16:52:00

On May 6, 3:38=A0pm, egadget1
<rnu...@gmail.com> wrote:
> Hi,
>
> =A0I have a basic question. =A0Is is possible in the xilinx ISE enviroment=

> to make a verilog wrapper of some VHDL code. =A0I don't want to recode
> it in verilog.
>
> Thanks
> Rob

Never mine I figured it out.

Rob

Re: Call VHDL module from Verilog - Mike Treseler - 2008-05-06 17:01:00

egadget1 wrote:

>>  I have a basic question.  Is is possible in the xilinx ISE enviroment
>> to make a verilog wrapper of some VHDL code.  I don't want to recode
>> it in verilog.
>>
>> Thanks
>> Rob
> 
> Never mind I figured it out.

The rule is, you have to tell us what you did ;)
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