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Comp.Arch.FPGA | Spartan3 interface with DDR SDRAM

There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

Spartan3 interface with DDR SDRAM - FP - 2008-06-05 10:24:00

I would like some suggestions on interfacing the
Xilinx Spartan3
device with a DDR SDRAM. The idea is to build a controller that will
set up the DDR-SDRAM so that I can do a burst read of a page of data
into a block of internal SRAM (dual port).

Your help is appreciated
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Re: Spartan3 interface with DDR SDRAM - 2008-06-05 11:47:00

On Jun 5, 7:24 am, FP
<FPGA.unkn...@gmail.com> wrote:
> I would like some suggestions on interfacing the Xilinx Spartan3
> device with a DDR SDRAM. The idea is to build a controller that will
> set up the DDR-SDRAM so that I can do a burst read of a page of data
> into a block of internal SRAM (dual port).
>
> Your help is appreciated


Xilinx has several design examples on their web site.

A google search turns up a few more on various sites.

You do know about burst length limitations with DDR devices?  You
can't burst a full page.

G.
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Re: Spartan3 interface with DDR SDRAM - Symon - 2008-06-05 11:51:00

"FP" <F...@gmail.com> wrote in message 
news:c...@a1g2000hsb.googlegroups.com...
>I would like some suggestions on interfacing the Xilinx Spartan3
> device with a DDR SDRAM. The idea is to build a controller that will
> set up the DDR-SDRAM so that I can do a burst read of a page of data
> into a block of internal SRAM (dual port).
>
> Your help is appreciated

STW or at least Xilinx's website.

http://www.xilinx.com/products/devkits/HW-SPAR3ADDR2-DK-UNI-G.htm
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