I would like to know if anyone here has already
done a VHDL code to
communicate/give commands to the LTC2624 Digital to Analog Converter
that has the Spartan-3A starterkit board.

I am not asking for the code specifically, but I would like your
feedback regarding to this problem:


I've a code, which in simulation seems to be all ok, all the timings
are met according to the timing specifications in the LTC2624 data
sheet (http://www.linear.com/pc/downloadDocument.do?
navId=H0,C1,C1155,C1005,C1156,P2048,D2170) .
The FPGA is configuring from one of the kit's SPI Flash PROM. When I
take the board to the oscilloscope and try to measure the voltage, it
is not working as expected. 0 voltage is read.

The rest features of the program, for example, communication with the
LCDisplay and LEDs, are all functioning. The UCF constraints are ok.

I don't have any more clue that could help me to solve this.

If you have worked with that Digital-to-Analog converter model in the
Xilinx Spartan-3A or other board having that model, please reply.
How did you manage to solve the problem, if all seemed ok with the
code, timing specifications, etc, but the resulting output voltage is
not working as expected [stays in 0]?


Thanks,
m  m

m m wrote:

> I would like to know if anyone here has already done a VHDL code to
> communicate/give commands to the LTC2624 Digital to Analog Converter
> that has the Spartan-3A starterkit board.

I have implemented a simple test for the Spartan 3E starter kit board,
which has the same DAC:

http://www.frank-buss.de/SignalGenerator/

-- 
Frank Buss, f...@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Thank you. I was comparing your code with mine,
and I see that the
signal DAC_CLR is always high, in your code. In my code I was not
setting/using that signal. I see that the DAC manual says:


"CLR (Pin 11): Asynchronous Clear Input. A logic low at
this level-triggered input clears all registers and
causes the DAC voltage outputs to drop to 0V for the LTC2604/LTC2614/
LTC2624."

=2E.. Perhaps that can be the problem why the output voltage is always
0..


Second, my code declares the architecture as Behavioral, not as RTL.


I still have not checked with the osilloscope, now that I modified.
I'll check on this week and post results here. Perhaps someone else
'is having' or 'will have' the same problem.



Thank you,
m m
_____________________________
On Aug 23, 6:47=A0pm, Frank Buss <f...@frank-buss.de> wrote:

> I have implemented a simple test for the Spartan 3E starter kit board,
> which has the same DAC:
>
> http://www.frank-buss.de/SignalGenerator/
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys=
tems.de

Thank you Sir. I checked on the oscilloscope and
now it is working as
expected.
I was missing that signal (dac_clr). Also, I was declaring the '12-bit
unsigned data' of the 'frame' as 'std_logic_vector' instead of
'unsigned'.


Thank you again,
m m
____________________________

On Aug 23, 6:47=A0pm, Frank Buss <f...@frank-buss.de> wrote:
>
> I have implemented a simple test for the Spartan 3E starter kit board,
> which has the same DAC:
>
> http://www.frank-buss.de/SignalGenerator/
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys=
tems.de

Hello 

I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't knowhow much I have to consider for SPI_SCK,should it be the same as my mainclk which is 50Mhz?

I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , IconsiderSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?should it besame? 	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface onhttp://www.FPGARelated.com

Hello 

I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't knowhow much I have to consider for SPI_SCK,should it be the same as my mainclk which is 50Mhz?

I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , IconsiderSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?should it besame? 	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface onhttp://www.FPGARelated.com

mlajevar wrote:

> I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know
> how much I have to consider for SPI_SCK,should it be the same as my main
> clk which is 50Mhz?

First see the datasheet of the LTC2624, if such a high clock is allowed.
But it doesn't make sense. Even if you want to update all 4 DACs with
different values, you'll need 96 bits and the maximum bandwith of the DACs
is 180 kHz, so the maximum required clock is 17 MHz. Create a clock which
is sufficient for your required output update rate. And it is much easier
to implement it with a DAC clock of 50MHz/n, with n>=2.

-- 
Frank Buss, f...@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de