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Comp.Arch.FPGA | Question: size of Stratix??

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Question: size of Stratix?? - Jian Liang - 2004-02-26 22:46:00

  I am looking for the die size of Stratix EP1s10
FPGA. It will be highly appreciated if anybody can give me a hint where to find such
information. Any number in terms of mm^2, lamda, transistor count or gate count will be
fine. I have checked the data sheet but could not find any.

Thanks for care!
Please reply to my email: j...@ecs.umass.edu
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Re: Question: size of Stratix?? - marise - 2004-02-27 00:05:00

I ran the testbench as shown below   <BR>
and even though it seems to be a simple piece of code ,I keep getting errors for the
syntax particularly opening files and closing them for reading or writing. I am using 3.1i
Foundation Xilinx with Synopsys synthesis tools.Apparently the textio package is for
simulation only and  was advised to use "synthesis on/off" <BR>
The code is as follows <p>library ieee; <BR>
use ieee.std_logic_1164.all; <p>library ieee; <BR>
USE IEEE.STD_LOGIC_TEXTIO.ALL; <BR>
use  std.textio.all <p>entity testbench is <BR>
generic( <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;vwidth :
INTEGER := 8); <p>end testbench; <p>architecture TB_ARCHITECTURE of testbench
is <BR>
component window_9 <BR>
generic( <BR>
vwidth : INTEGER := 8 <BR>
&nbsp;); <p>port( <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Clk: in
STD_LOGIC; <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RSTn: in
STD_LOGIC; <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D: in 
std_logic_vector (vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w11: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w12: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w13: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w21: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w22: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w23: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w31: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w32: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w33: out
std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DV: out
STD_LOGIC <BR>
&nbsp;&nbsp;&nbsp;&nbsp;); <BR>
end component; <p> signal       Clk:  STD_LOGIC; <BR>
&nbsp;signal        RSTn:  STD_LOGIC; <BR>
signal         D: std_logic_vector(vwidth-1 downto 0); <BR>
signal         w11:  std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;signal        w12:  std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;signal        w13:  std_logic_vector(vwidth-1 downto 0); <BR>
signal         w21:  std_logic_vector(vwidth-1 downto 0); <BR>
signal         w22: std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;signal        w23: std_logic_vector(vwidth-1 downto 0); <BR>
signal         w31:  std_logic_vector(vwidth-1 downto 0); <BR>
signal         w32:  std_logic_vector(vwidth-1 downto 0); <BR>
&nbsp;signal        w33:  std_logic_vector(vwidth-1 downto 0); <BR>
signal         DV:  STD_LOGIC; <p>begin <p>         UUT : window_9 <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;port map <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;(  <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Clk=&g
t;Clk, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RSTn=&
gt;RSTn, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D=&gt;
D, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w11=&g
t;w11, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w12=&g
t;w12, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w13=&g
t;w13, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w21=&g
t;w21, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w22=&g
t;w22, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w23=&g
t;w23, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w31=&g
t;w31, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w32=&g
t;w32, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;w33=&g
t;w33, <BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DV=&gt
;DV ); <p><p>        read_from_file: process(Clk) <BR>
variable indata_line: line; <BR>
variable indata: integer; <p>file input_data_file: text open read_mode is
"lena.bin"; <BR>
--file input_data_file: text is in "A:/lena.bin"; <BR>
begin <BR>
if rising_edge(Clk) then <BR>
readline(input_data_file,indata_line); <BR>
read(indata_line,indata); <BR>
D &lt;= conv_std_logic_vector(indata,8); <BR>
if endfile(input_data_file) then <BR>
report "end of file -- looping back to start of file"; <BR>
file_close(input_data_file); <BR>
--return; <BR>
--file input_data_file: text is in "A:/lena.bin"; <BR>
file_open(input_data_file,"lena.bin"); <BR>
end if; <BR>
end if; <BR>
end process; <BR>
write_to_file: process(Clk) <BR>
variable outdata_line: line; <BR>
variable outdata: integer:=0; <BR>
file output_data_file: text open write_mode is "vhdl_output.bin"; <BR>
--file output_data_file:text is out "vhdl_output.bin"; <BR>
begin <BR>
if rising_edge(Clk) then <BR>
outdata := CONV_INTEGER(unsigned(w11)); <BR>
if DV = '1' then <BR>
write(outdata_line,outdata); <BR>
writeline(output_data_file,outdata_line); <BR>
end if; <BR>
end if; <BR>
end process; <p>clock_gen: process <BR>
begin <BR>
Clk &lt;= '0'; <BR>
wait for 5 ns; <BR>
Clk &lt;= '1'; <BR>
wait for 5 ns; <BR>
end process; <BR>
reset_gen: process <BR>
begin <BR>
RSTn &lt;= '0'; <BR>
wait for 10 ns; <BR>
RSTn &lt;= '1'; <BR>
wait; <BR>
end process; <BR>
end TB_ARCHITECTURE; <BR>
--synopsys translate_off <p>configuration cfg_TESTBENCH_WINDOW9 of testbench  is
<BR>
&nbsp;&nbsp;&nbsp;&nbsp;for TB_ARCHITECTURE <BR>
&nbsp;&nbsp;&nbsp;&nbsp;for all : window_9 <BR>
&nbsp;&nbsp;&nbsp;&nbsp;use configuration work.cfg_window_9; <BR>
&nbsp;&nbsp;&nbsp;&nbsp;end for; <BR>
end for; <BR>
&nbsp;&nbsp;end configuration cfg_TESTBENCH_WINDOW9 ;   <BR>
&nbsp;&nbsp;--synopsys translate_on
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