Hi

I am new to ASIC prototyping approaches. I know it concept wise but
want to know more about how popular is it among designers. In other
words, is it a commonly taken path for verification or is more of a
concpet than having practical applictaions.

I also want to know if there are any tools specifically designed for
ASIC prototyping and how mature they are about the hanlding of issues
that will come up during the interfaces of different FPGA on boards.

--
Edwin Gobain

<e...@gmail.com> wrote in message 
news:6...@s28g2000prd.googlegroups.com...
> Hi
>
> I am new to ASIC prototyping approaches. I know it concept wise but
> want to know more about how popular is it among designers.

A Dataquest survey from 2005 showed that 40% of all ASIC's are prototyped on 
FPGA's. However, given the current cost and size of modern FPGA's I wouldn't 
be surprised if that number is now doubled.

> In other
> words, is it a commonly taken path for verification or is more of a
> concpet than having practical applictaions.
>
> I also want to know if there are any tools specifically designed for
> ASIC prototyping and how mature they are about the hanlding of issues
> that will come up during the interfaces of different FPGA on boards.

You need a synthesis tool that can handle an ASIC netlist (gated clocks, 
Synopsys Design Constraint, Designware support) examples are Mentor's 
Precision and Synplicity's Synplify. You also need a partitioner that can 
map your large synthesised netlist onto multiple FPGA's. Examples are ACE 
from Auspy, Chipit Manager from Prodesign, Certify from Synplicity). To get 
more info check out the top 3 (?) prototyping vendors Hardi, Prodesign and 
Dini.

http://www.uchipit.com/ce/index.htm
http://www.dinigroup.com/DN5000k10.php
http://www.synplicity.com/products/haps/

Hans
www.ht-lab.com


>
> --
> Edwin Gobain 

e...@gmail.com writes:

> I am new to ASIC prototyping approaches. I know it concept wise but
> want to know more about how popular is it among designers. In other

I would say that it's quite popular. However, you want it to be as
transparent as possible. You would like it to behave like a fast
simulator (which is a *lot* cheaper, but your observability is
somewhat limited compared to simulation). But you will typically find
yourself spending considerable amount of time optimizing your design
to make the timing requirements. If you interface to some standard bus
like PCIe or similar you have to make the speed requirements. But if
you interface only to yourself you might be able to scale the
"simulation" down without having to meet the requirements of other
interfaces.

Petter
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