Hi, Im new to DSP stuff and have a very simple
question.

Since the multiplier in virtex 5 dsp is 2's complement ... does that
mean when using the std_logic_unsigned library, the maximum number of
bits A input can have is 24 instead of 25 and 17 instead of 18 for B
input?

Whereas I can use 25 bits for A and 18 for B by using the
std_logic_signed library?

thanks.

<h...@gmail.com> wrote in message 
news:a...@u40g2000pru.googlegroups.com...
> Hi, Im new to DSP stuff and have a very simple question.
>
> Since the multiplier in virtex 5 dsp is 2's complement ... does that
> mean when using the std_logic_unsigned library, the maximum number of
> bits A input can have is 24 instead of 25 and 17 instead of 18 for B
> input?
>
> Whereas I can use 25 bits for A and 18 for B by using the
> std_logic_signed library?
>
> thanks.

Dear 'new to DSP stuff',

Although this doesn't answer your question, you should be using numeric.std

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

HTH., Syms. 

On Oct 21, 8:43 pm, hanumaa...@gmail.com wrote:
> Hi, Im new to DSP stuff and have a very simple question.
>
> Since the multiplier in virtex 5 dsp is 2's complement ... does that
> mean when using the std_logic_unsigned library, the maximum number of
> bits A input can have is 24 instead of 25 and 17 instead of 18 for B
> input?
>
> Whereas I can use 25 bits for A and 18 for B by using the
> std_logic_signed library?
>
> thanks.

In the Virtex 5 FPGA XtremeDSP Design Considerations document, it's
stated that unsigned multiplication is performed by setting the MSB of
the inputs to 0, thus only giving you 24 and 17 bits. Regardless of
which library you use, that is the hard limit for each multiplier, but
you can perform larger unsigned multiplies if you're willing to build
them out of multiple XtremeDSP slices or the general FPGA logic
fabric, though of course you'll consume a lot of generic logic to
produce multipliers.

The logic synthesizer will infer the number of multipliers required to
implement a given multiply operation as defined in your VHDL so you
don't have to restrict the size of the operands, though of course you
should be aware of your resource usage.

Darol Klawetter

On Wed, 22 Oct 2008 07:39:23 +0100
"Symon" <s...@hotmail.com> wrote:

> 
> <h...@gmail.com> wrote in message 
> [snip]
> 
> Dear 'new to DSP stuff',
> 
> Although this doesn't answer your question, you should be using
> numeric.std
> 
> http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf
> 
> HTH., Syms. 
> 
> 

Though this leads me back to a question that, while I'm sure it's been
asked before, still confuses me.  Does anyone know why Xilinx in both
their documentation and auto-templatey-thingies continues to push
people towards std_logic_arith and its kin rather than numeric_std? 

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

"Rob Gaddi"
<r...@technologyhighland.com> wrote in message 
news:20081022094321.b200dea6.r...@technologyhighland.com...
>>
>
> Though this leads me back to a question that, while I'm sure it's been
> asked before, still confuses me.  Does anyone know why Xilinx in both
> their documentation and auto-templatey-thingies continues to push
> people towards std_logic_arith and its kin rather than numeric_std?
>

Rob,
http://www.safetycenter.navy.mil/Articles/a-m/monkeys.htm
HTH., Syms. 

Rob Gaddi wrote:

> Though this leads me back to a question that,
> while I'm sure it's been asked before,

Yes:
http://groups.google.com/groups/search?q=library+madness+zhiquan

> Does anyone know why Xilinx in both
> their documentation and auto-templatey-thingies continues to push
> people towards std_logic_arith and its kin rather than numeric_std? 

1. Old habits die hard.
2. Old examples never die.
3. The margins on devices are better
   than the margins on tools.

Actually, std_logic_arith is the least evil
of the old synopsis libraries, because it
at least allowed signed and unsigned vectors
to be used in the same expression.
It also left the std_logic_vector
comparison functions alone.

Problems arise when I try to use a
library like std_logic_signed
          or std_logic_unsigned
that declare conflicting math and comparison functions
for std_logic_vector.

Details here:
 http://www.vhdl.org/rassp/vhdl/guidelines/vhdlqrc.pdf
 http://www.vhdl.org/rassp/vhdl/guidelines/1164qrc.pdf

       -- Mike Treseler