Hello all,

Is there a way (even a rough approach) of finding an equivalent
estimate of ASIC Gates for the design implemented in Xilinx FPGAs
considering their definitions of Slices, DSPs and BRAMs? I know the
approximate conversion ratio between ASIC and FPGA gates is 1:5, but
way of identifying gates used in FPGA implementation is unknown
(atleast for the latest families to be implemented on ISE 10.1).

I am sure some of you would have had this practical experience and I
will be glad if someone throws some light on my query.

Thanks in advance.

Venkat.

Venkat wrote:

> Is there a way (even a rough approach) of finding an equivalent
> estimate of ASIC Gates for the design implemented in Xilinx FPGAs
> considering their definitions of Slices, DSPs and BRAMs? I know the
> approximate conversion ratio between ASIC and FPGA gates is 1:5, but
> way of identifying gates used in FPGA implementation is unknown
> (atleast for the latest families to be implemented on ISE 10.1).

There is no good way.  For ASICs the usual way is to count the
transistors and divide by the transistors in a two input NAND
gate (four for CMOS).

> I am sure some of you would have had this practical experience and I
> will be glad if someone throws some light on my query.

For FPGAs, Xilinx (and others) count DSPs and BRAMs as the appropriate
number of gates, but you might not be able to use them in your design.

For CLBs, you can use one for just one inverter, or an N input XOR
gate (probably the most complicated gate).   Designs will generally
not fill up all the CLBs, though might come close.  They all count
toward the gate count.  Routing takes up much of an FPGA, but,
at least traditionally, doesn't count at all.

Does that help?

-- glen

On 2008-12-05, Venkat
<v...@gmail.com> wrote:
> I am sure some of you would have had this practical experience and I
> will be glad if someone throws some light on my query.

As others have already said, this ratio is not going to be very
accurate. Just a few data points to illustrate this:


A 32 bit registered adder:
  * Synthesized for 130nm process, optimized for area: 2400
  * Synthesized for 130nm process, optimized for speed: 11700
  * Number of LUTs in a Virtex-4: 32

A 32-bit 16-to-1 registered mux:
  * Synthesized for 130nm process, optimized for area: 5600
  * Synthesized for 130nm process, optimized for speed: 6700
  * Number of LUTs in a Virtex-4: 256

An 8-bit 16 entry synchronuous register file memory (one port):
  * Synthesized for 130nm process, optimized for area: 7700
  * Synthesized for 130nm process, optimized for speed: 8300
  * Number of LUTs in a Virtex-4: 8

(Area figures in square micrometers)


The conclusion from these values is that the ratio between
Slices and ASIC area is going to vary wildly from design to
design. Even if you try to make your algorithm clever by looking
at the kind of structure (mux, adder, memory, etc) and figure out
a gate count for that kind of structure in the FPGA, your figures
will still vary wildly depending on if that particular component in
the FPGA is a part of the critical path or not. And if you try to take
that into account, well, you might as well synthesize your design with
an ASIC synthesis tool and get much more accurate numbers. (Even so,
the backend tool will probably add area to the estimates from the
synthesis tool in my experience.)

Anyway, as others have said, it is likely that memories will be your
biggest cost in the ASIC. After memories, it is also likely that your
I/O pads might be a big cost. Multipliers can also be quite costly.
In one of the two ASICs I have been involved in (a research DSP for
MP3 decoding), the area cost of the logic is probably about the same
as for the I/O pads whereas the memories consume the major part of
the silicon die.

/Andreas

Venkat wrote:
> Is there a way (even a rough approach) of finding an equivalent
> estimate of ASIC Gates for the design implemented in Xilinx FPGAs
> considering their definitions of Slices, DSPs and BRAMs? I know the
> approximate conversion ratio between ASIC and FPGA gates is 1:5, but
> way of identifying gates used in FPGA implementation is unknown
> (atleast for the latest families to be implemented on ISE 10.1).

There is no easy way. First thing to figure out is that is your design
gate of memory limited. If it is memory limited just estimate the
silicon area of the memories. The process documentation gives estimates
how many sq.mm each megabit of ram takes etc. Or use the memory
generators to generate the memories for that process (use as big
memories instances as possible to get more density etc.). The dies I
have seen are usually almost full of memory, the logic is tiny part
of the die, with 1Mgate/mm^2 it hard to fill the chip with logic.

For the logic it might be easiest to just run the design trough Synopsys
DC etc. to get rough estimate of the gate count. If that is not possible
just multiply the LUT count by ~five and figure out some estimates for
the multipliers if they are used in the DSP blocks. You should be near
enough after that stage. You have to remember that hold fixing etc. can
easily add 10% cells to the design during p&r etc. Also ASIC synthesis
might create quite different structures, and that makes the comparison
more difficult. In ASIC for example you might need much less replication
because in comparable process ASIC is at least 3-5x faster.

--Kim

On 5 Dec, 00:51, Glen Herrmannsfeldt
<g...@ugcs.caltech.edu> wrote:
> Venkat wrote:
> > Is there a way (even a rough approach) of finding an equivalent
> > estimate of ASIC Gates for the design implemented in Xilinx FPGAs
> > considering their definitions of Slices, DSPs and BRAMs? I know the
> > approximate conversion ratio between ASIC and FPGA gates is 1:5, but
> > way of identifying gates used in FPGA implementation is unknown
> > (atleast for the latest families to be implemented on ISE 10.1).
>
> There is no good way. =A0For ASICs the usual way is to count the
> transistors and divide by the transistors in a two input NAND
> gate (four for CMOS).

Or, take the total cell area and divide by the area of a low drive
strength two input NAND.

Jon

On 5 =D7=93=D7=A6=D7=9E=D7=91=D7=A8, 14:25, Jon
Beniston <j...@beniston.com=
> wrote:
> On 5 Dec, 00:51, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>
> > Venkat wrote:
> > > Is there a way (even a rough approach) of finding an equivalent
> > > estimate of ASIC Gates for the design implemented in Xilinx FPGAs
> > > considering their definitions of Slices, DSPs and BRAMs? I know the
> > > approximate conversion ratio between ASIC and FPGA gates is 1:5, but
> > > way of identifying gates used in FPGA implementation is unknown
> > > (atleast for the latest families to be implemented on ISE 10.1).
>
> > There is no good way.  For ASICs the usual way is to count the
> > transistors and divide by the transistors in a two input NAND
> > gate (four for CMOS).
>
> Or, take the total cell area and divide by the area of a low drive
> strength two input NAND.
>
> Jon

I would start with the xilinx map report:
Design Summary:

Logic Utilization:

Number of Slice Flip Flops: 324 out of 21,504 1%

Number of 4 input LUTs: 2,288 out of 21,504 10%

....
Total equivalent gate count for design: 29,960
The example is atken from:
http://bknpk.no-ip.biz/cpu_8051_ver/top.html

On Dec 4, 5:41 pm, Venkat
<venkat.ja...@gmail.com> wrote:
> Hello all,
>
> Is there a way (even a rough approach) of finding an equivalent
> estimate of ASIC Gates for the design implemented in Xilinx FPGAs
> considering their definitions of Slices, DSPs and BRAMs? I know the
> approximate conversion ratio between ASIC and FPGA gates is 1:5, but
> way of identifying gates used in FPGA implementation is unknown
> (at least for the latest families to be implemented on ISE 10.1).
>
> I am sure some of you would have had this practical experience and I
> will be glad if someone throws some light on my query.
>
> Thanks in advance.
>
> Venkat.

Only one way that will give you usable numbers:  Send your files to
your ASIC vendor and ask "About how many gates does this synthesize
to?"

On Dec 6, 5:22=A0am, LittleAlex
<alex.lo...@email.com> wrote:
> On Dec 4, 5:41 pm, Venkat <venkat.ja...@gmail.com> wrote:
>
> > Hello all,
>
> > Is there a way (even a rough approach) of finding an equivalent
> > estimate of ASIC Gates for the design implemented in Xilinx FPGAs
> > considering their definitions of Slices, DSPs and BRAMs? I know the
> > approximate conversion ratio between ASIC and FPGA gates is 1:5, but
> > way of identifying gates used in FPGA implementation is unknown
> > (at least for the latest families to be implemented on ISE 10.1).
>
> > I am sure some of you would have had this practical experience and I
> > will be glad if someone throws some light on my query.
>
> > Thanks in advance.
>
> > Venkat.
>
> Only one way that will give you usable numbers: =A0Send your files to
> your ASIC vendor and ask "About how many gates does this synthesize
> to?"

Thank you all for the patient responses.

It was very helpful to learn more on this. I personally did some
analysis
on the gate count equivalent by running varieties of designs on the
Xilinx
FPGA and would like to share the results here.

1 LUT approximates to 10 FPGA Gates
1 FF approximates to 4 FPGA Gates

Usage of BRAM utilizes 16Kb RAM by default irrespective of the size
of memory used and each bit of memory utilizes 4 FPGA Gates and
hence if the in-built Block RAM is used, it ends up with 65,536 Gates.

DSP resources are more tricky as they do not show up as added gates
in the Post-Map Result in earlier ISE Versions. To make the
multipliers
using the Logic shows some idea of the gate count.

A 16x16 Multiplier uses about 4000 Gates which is halved for a 12x12
multiplier.

So the rough way to approximate the gate count is to use the FF, LUTs,
BRAMs
and DSPs as reference and work out the sum.

Thanks again for the responses.

Venkat.

On 2008-12-08, Venkat
<v...@gmail.com> wrote:
> 1 FF approximates to 4 FPGA Gates

Have you considered the fact that a commercial ASIC would probably
need some sort scan-chain that almost all flip-flops in the chip
will be connected to? (For chip testing purposes.) If so, 4 gates
sounds quite small for an estimate of the gate cost in an ASIC.

>
> Usage of BRAM utilizes 16Kb RAM by default irrespective of the size
> of memory used and each bit of memory utilizes 4 FPGA Gates and
> hence if the in-built Block RAM is used, it ends up with 65,536 Gates.

I assume you are calculating the gate count to figure out the area cost.
If so, does your calculation for these values consider the fact that
the storage elements in a block-ram is usually very optimized when
compared to normal flip-flops?

/Andreas