I'm looking into a crosspoint switching
application where
it appears FPGA's are the best choice even though I won't
use much of the internals.  What I'm looking for is the
best price per I/O pin of relatively fast parts.  Newer
releases of FPGA seem to target better price per logic cell
rather than I/O so I've already noticed that from Xilinx
I can do better with Spartan 2e than Spartan 3 in terms of
cost per I/O pin.  Obviously smaller parts in each family
also giver better price per I/O because there are more
I/O's per logic cell.  Any suggestions for a better price
would be appreciated.

Also the reason I'm not currently looking at CPLD's is that
the application requires soft upload and I don't want parts
with limited programming cycle life (EPROM or FLASH based).
256 I/O's per part is a good match for the design although
even at this level I will need multiple parts.  Right now
I'm more interested in what family to use for the best price
per I/O and then I'll pick the device size that fits best.

Hi Gabor,

You may want to consider the Altera Cyclone EP1C4 device.  This device uses
a staggered pad ring to deliver more I/Os (and consequently fewer LEs) in a
given die size than the other Cyclone members.  The device is available in
324- and 400-pin FBGA packages giving you 249 and 301 user I/Os to work with
respectively.  I know nothing about pricing beyond what is on our main
website ($7.50 based on 250K unit volumes in 2004 time frame) -- I'd suggest
you contact an Altera distributer or sales rep to investigate cost.

Go to http://www.altera.com/cyclone for more details on the Cyclone family.

Regards,

Paul Leventis
Altera Corp.

On 1 Apr 2004 06:19:47 -0800, g...@alacron.com
(Gabor Szakacs) wrote:
>I'm looking into a crosspoint switching application where
>it appears FPGA's are the best choice even though I won't
>use much of the internals.  What I'm looking for is the
>best price per I/O pin of relatively fast parts.  Newer
>releases of FPGA seem to target better price per logic cell
>rather than I/O so I've already noticed that from Xilinx
>I can do better with Spartan 2e than Spartan 3 in terms of
>cost per I/O pin.  Obviously smaller parts in each family
>also giver better price per I/O because there are more
>I/O's per logic cell.  Any suggestions for a better price
>would be appreciated.
>
>Also the reason I'm not currently looking at CPLD's is that
>the application requires soft upload and I don't want parts
>with limited programming cycle life (EPROM or FLASH based).
>256 I/O's per part is a good match for the design although
>even at this level I will need multiple parts.  Right now
>I'm more interested in what family to use for the best price
>per I/O and then I'll pick the device size that fits best.

Given your application, you may want to review a paper presented
at the 2003 FCCM conference:

  A High I/O Reconfigurable Crossbar Switch

	Steve Young, Peter Alfke, ColmFewer, Scott McMillan,
	Brandon Blodget, and Delon Levi

The procedings are available through the IEEE, but maybe you can
get a copy directly from the authors, who are all at Xilinx.
Peter Alfke is a regular on this news group.




Philip Freidin
Fliptronics

The Spartan 3 also uses a staggered IO ring.

http://direct.xilinx.com/bvdocs/publications/ds099-1.pdf

on page 4 of 5 lists all of the package IO combinations.

For the 320 and 456 pin packages, we have 221, and 333 IOs.  Prices 
ranges from $6.50 to $12 in large qty right now (2004).

Austin