Hi everybody, Could you people help me choose
between Altera's Stratix
and Xilinx Vertex II...also as how to analyze the datasheet to
conclude the pros and cons of both the architectures?
thanks
-andy

Andy,

What are you trying to do?

It is very hard to compare something when no one knows what the 
application is.

For example, if you need embedded ultra low power 32 bit RISC >400 MIPs 
processors, there is no choice other than VII Pro with up to two IBM 
405PPC (tm).

Or, if you need twenty 10 Gbs interfaces, there is no choice other than 
the 2VP70X.

And we misspell it Virtex(tm) on purpose so we could trademark the name.

Austin

Andy wrote:

> Hi everybody, Could you people help me choose between Altera's Stratix
> and Xilinx Vertex II...also as how to analyze the datasheet to
> conclude the pros and cons of both the architectures?
> thanks
> -andy

How do you choose between a Toyota and a Honda,
or between a Mercedes and a
BMW ? You have to study the documentation, and get beyond the common
features, then evaluate the differences, and find out what's most important
tofor you.
You might also read the marketing literature, but you have to realize that
marketeers will only dwell on the positive aspects, and they might
occasionally even stoop so low to exaggerate...
It's Application's never-ending job to keep them honest.
Peter Alfke
======================================
> From: a...@yahoo.com (Andy)
> Organization: http://groups.google.com
> Newsgroups: comp.arch.fpga
> Date: 2 Apr 2004 11:09:14 -0800
> Subject: vertex II vs Stratix
> 
> Hi everybody, Could you people help me choose between Altera's Stratix
> and Xilinx Vertex II...also as how to analyze the datasheet to
> conclude the pros and cons of both the architectures?
> thanks
> -andy

On 2 Apr 2004 11:09:14 -0800, a...@yahoo.com
(Andy) wrote:

>Hi everybody, Could you people help me choose between Altera's Stratix
>and Xilinx Vertex II...also as how to analyze the datasheet to
>conclude the pros and cons of both the architectures?
>thanks
>-andy

If you have a design underway, one method is to take a representative
chunk of that design and implement it, using the free tools (or the real
tools with an evaluation license) for that architecture. I needed
arithmetic, so I chose a square root unit as a non-trivial test.

That will give you a basis for comparing gate counts, speed, capacity,
-and the reliability and usefulness of the tools- for both
architectures.

- Brian

Hi, Andy,

There are many things that will affect the optimal FPGA selection for
your design including core performance, DSP capability, high-speed
memory interfaces, clocking requirements, etc. not to mention the
vendor specific development tools.  I have been working on
benchmarking Altera versus Xilinx and there are varieties of design
and tool flow issues that will affect your result.

When you benchmark, you will need to control the tool effort level
(fast or exhaustive), software settings, timing constraints and clocks
analyzed.  These settings can cause results to change by up to 3X
based on our benchmarks so understanding these options is fundamental
to making a good performance comparison.  In addition, you will need
to be careful if your design is coded to take advantages of specific
features in a FPGA.

These issues will be discussed in a net seminar hosted by Altera on
April 8th regarding effective FPGA performance benchmarking
methodology and comparison of leading FPGA architectures.  If you are
interested, the registration link is here:

http://www.altera.com/education/net_seminars/current/ns_0408.html

John Hu
Altera Corp.


a...@yahoo.com (Andy) wrote in message
news:<1...@posting.google.com>...
> Hi everybody, Could you people help me choose between Altera's Stratix
> and Xilinx Vertex II...also as how to analyze the datasheet to
> conclude the pros and cons of both the architectures?
> thanks
> -andy

All,

Benchmarks can be organized to demonstrate just about anything you want. 
  We try to be as fair as possible, as we are interested in evaluating 
the strengths of the competition, not just the weaknesses.

Caution!

Since the VII Pro is 40% faster than Stratix, and Stratix Two will be 
(as claimed, once they have silicon and test it) to be 50% faster than 
Stratix One, that makes Stratix Two roughly at parity with Virtex II Pro 
from Altera's claims when compared against our extensive 200+ 
simulations of customer designs thru both sets of tools using real 
speeds files from 2+ years of silicon.

We will release the results of our suite of 200+ actual customer designs 
  results being pushed thru the respective tools soon.  So at that 
seminar, ask:

how many designs?
where did they come from?
do they target device specific features?
how much of the part is being used?
what is the speed data based on?

If the answers are not: 200+, customers, yes, all (>80%), and real 
silicon, then 'caveat emptor'.

So, for what it is worth, the two parts look like they are going to be 
roughly equivalent in fabric performance.

Virtex II Pro also has (today) the 405PPC, the MGTs, the DCMs, and the 
SRL16s.

One maxim of marketing is to take whatever you think you are strong in, 
and the competitor is weak in (real or imagined), and make that the 
issue.  Don't talk about anything else.  Bang the drum with a loud and 
consistent message.  Hey, that is fair.  If the fabric is predicted to 
be at parity, or slightly better, make a big deal out of it.

I prefer to analyse all the strengths and weaknesses as an engineer, and 
see how that relates to my application.

Stratix Two will be 90nm technology.

Virtex II Pro is 130 nm, and going on 2 1/2 years old right now.

Virtex 4 (the 90nm version) is yet to be revealed, and that would be the 
real apples to apples product face-off.  In my opinion, the 90nm parts 
should outperform the 130 nm parts (or why bother?).  The dissapointment 
is that it appears that it will be only one speed grade faster in the 
fabric, and still lack many features.  So, if you want speed, just order 
one speed grade faster in 130 nm today!

Austin

Austin Lesea <a...@xilinx.com> wrote:
> All,
> 
> Benchmarks can be organized to demonstrate just about anything you want. 
>   We try to be as fair as possible, as we are interested in evaluating 
> the strengths of the competition, not just the weaknesses.
> 
> Caution!
> 
> Since the VII Pro is 40% faster than Stratix, and Stratix Two will be 
> (as claimed, once they have silicon and test it) to be 50% faster than 
> Stratix One, that makes Stratix Two roughly at parity with Virtex II Pro 
> from Altera's claims when compared against our extensive 200+ 
> simulations of customer designs thru both sets of tools using real 
> speeds files from 2+ years of silicon.
> 
> We will release the results of our suite of 200+ actual customer designs 
>   results being pushed thru the respective tools soon.  So at that 
> seminar, ask:
> 
> how many designs?
> where did they come from?
> do they target device specific features?
> how much of the part is being used?
> what is the speed data based on?
> 
> If the answers are not: 200+, customers, yes, all (>80%), and real 
> silicon, then 'caveat emptor'.

URKH! Do we really need aggresive marketing wars in this newsgroup?


-- 
	Sander

+++ Out of cheese error +++

Sander,

I apologize if I have offended.  Just wanted to be sure to balance the 
scales.

Austin

I agreed.  I was in Altera web seminar.  I asked
"Stratix is only
comparable to Virtex-II, not -Pro" and did not get answer.

I do not have comments on the performance comparison materials.  But
my designs required 190 16x16 multipiliers in each of three FPGAs in a
row.  Stratix had no way to do it.  Stratix-II, too later.

I really think Xilinx's claims ISE 6.2 40% over 6.1 50% over 5.2 70%
over 4.x ..... were jokes.  I was seeing -1000% 6.2 over 6.1.

-qlyus


Austin Lesea <a...@xilinx.com> wrote in message
news:<c51n66$d...@cliff.xsj.xilinx.com>...
> Sander,
> 
> I apologize if I have offended.  Just wanted to be sure to balance the 
> scales.
> 
> Austin

Austin Lesea <a...@xilinx.com> wrote:
> Sander,
> 
> I apologize if I have offended.  Just wanted to be sure to balance the 
> scales.

no offence, I just think pure marketing - and even more so aggressive 
marketing asking people to question various things doesn't IMHO really 
belong here. This isn't to pick on Xilinx or you.

> 
> Austin
> 

-- 
	Sander

+++ Out of cheese error +++