Hi,

I am designing a system which needs multiple interfaces (about 16) to
backplane running at about ~700Mhz. These are going to be source
synchronous interfaces and clock will be available.  I did not wanted
to use the build in transceivers because the 20 transceiver devices
are very expensive. The logic and block Ram requirement of the design
is relatively small.

I was wondering if for Xilinx FPGA can I use the normal LVDS select IO
pins to drive the backplane. Will it work? Are there any design
consideration that I need to take to accomplish this. What is the
maximum trace that the select LVDS IO can drive.

Also wondering if there is any difference between Xilinx and Altera
LVDS, if either or one of them is suited for backplane applications.

Cheers.

--
Goli

Hello,

These questions are essentially impossible to answer. You need to
figure out what sort of backplane you're working on, what sort of
board will be driving the backplane, and what sort of board will be
receiving the LVDS signal. Next, target a particular family of FPGA
rather than "Xilinx FPGA". After that, spend some time with minimally
HyperLynx or preferably an electromagnetic field simulator to figure
out if this is possible or not. I think you will find that noone will
give you a definitive answer other than "if you don't do your
homework, this will not work."

Good luck,

Nathan

On Mar 24, 2:16=A0am, Goli <tog...@gmail.com> wrote:
> Hi,
>
> I am designing a system which needs multiple interfaces (about 16) to
> backplane running at about ~700Mhz. These are going to be source
> synchronous interfaces and clock will be available. =A0I did not wanted
> to use the build in transceivers because the 20 transceiver devices
> are very expensive. The logic and block Ram requirement of the design
> is relatively small.
>
> I was wondering if for Xilinx FPGA can I use the normal LVDS select IO
> pins to drive the backplane. Will it work? Are there any design
> consideration that I need to take to accomplish this. What is the
> maximum trace that the select LVDS IO can drive.
>
> Also wondering if there is any difference between Xilinx and Altera
> LVDS, if either or one of them is suited for backplane applications.
>
> Cheers.
>
> --
> Goli

I have worked on LVDS over similar distances, and
bus wide backplane
structures, but only in 400-500Mbit/s zone. It worked fine in those
circumstances. Main consideration is to avoid skew in pair length and
between pairs if using multiple pairs. Matching will make data
recovery simple. Using a source synchronous clock roiuted with data
will also make life a lot easier.

Ultimately the trace capacitance will probably be the limiting thing
and a trade of speed versus maximum length will exist. Ensuring that
the the 2 traces of a pair run togther as much as possible will be
important. Minimising discontinuities like connectors is good
practise.

John Adair
Enterpoint Ltd.

On 24 Mar, 06:16, Goli <tog...@gmail.com> wrote:
> Hi,
>
> I am designing a system which needs multiple interfaces (about 16) to
> backplane running at about ~700Mhz. These are going to be source
> synchronous interfaces and clock will be available. =A0I did not wanted
> to use the build in transceivers because the 20 transceiver devices
> are very expensive. The logic and block Ram requirement of the design
> is relatively small.
>
> I was wondering if for Xilinx FPGA can I use the normal LVDS select IO
> pins to drive the backplane. Will it work? Are there any design
> consideration that I need to take to accomplish this. What is the
> maximum trace that the select LVDS IO can drive.
>
> Also wondering if there is any difference between Xilinx and Altera
> LVDS, if either or one of them is suited for backplane applications.
>
> Cheers.
>
> --
> Goli