Hi

I'm considering the option of converting an FPGA design into ASIC, but
have no experience with that.  My questions are:

1) Cost savings, how do ASICs compare to FPGAs?

2) Given VHDL that works on FPGA, will there be considerable risk
associated with the ASIC conversion?

3) How long can it take to have working chips?

4) Who can do it?  Do you have any recommendation?

Thanks a lot!

Regards,
Marc

On Wed, 29 Apr 2009 10:08:31 -0700 (PDT),
j...@hotmail.com wrote:

>Hi
>
>I'm considering the option of converting an FPGA design into ASIC, but
>have no experience with that.  My questions are:
>
>1) Cost savings, how do ASICs compare to FPGAs?
>
ASICs are very high NRE and low incremental unit cost so to get any
cost saving at all you have to get a large number of chips made. As a
first approximation you can assume that you'll have to spend $1M to
get an ASIC made and say $1 per chip after that. To get any cost
savings you need to buy ~1M/X (where $X is per fpga you're buying
now). If you're buying $50 FPGAs, you need 20K of them just to break
even (barely). Are you close to that number?

>2) Given VHDL that works on FPGA, will there be considerable risk
>associated with the ASIC conversion?
>
Yes. See my answer to the first question before asking for a list.

>3) How long can it take to have working chips?
>
Depending on the size of the design 6 to 9 months (3+ months from
tape-out to packaged chips, the rest for porting and verification)

>4) Who can do it?  Do you have any recommendation?

Lot companies do this for a living. We have done it a couple of times.
Try: http://www.google.com/#hl=en&q=fpga+to+asic+conversion

-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

j...@hotmail.com writes:

> 2) Given VHDL that works on FPGA, will there be considerable risk
> associated with the ASIC conversion?

Yes. RAM's, PLL's, and IO buffers will be different. Any IP you use
might not be available in a compatible part (microblaze, nios, bus
interfaces, etc). The gates are different so timing will be different.

Mostly you will have to do production test vectors in order to test
your chips. Altera and Xilinx have done this for you with your FPGA's.

You need a set of new tools and learn how to use them. ASIC synthesis
tools (dc), timing analyzers (primetime), ATPG etc. The tools are
expensive and takes time to learn.

> 3) How long can it take to have working chips?

It depens... 

> 4) Who can do it?  Do you have any recommendation?

Maybe Altera Hardcopy could be a good start for you? The savings is
not as great for high volumes, but the risk is lower and Altera does
most of the work for you.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

j...@hotmail.com wrote:
> I'm considering the option of converting an FPGA design into ASIC, but
> have no experience with that.  My questions are:

If you don't have any experience in ASIC design, then hire someone that
has. ASIC design is quite different compared to FPGA design and there
are many more steps.

Easiest way to do this is to hire a company that does this for living.
They have the knowledge, tools, experience with ASIC vendors etc.
They can also give some estimates if the project is worthwhile.
But even then you will need someone with ASIC experience, to speak
the same language with the company.

> 1) Cost savings, how do ASICs compare to FPGAs?

There is no answer to this. This depends on the selected process,
design size, package, volume, your relationship with the vendor
etc.

For example high IO count packages are expensive, and in
some cases FPGA might be more cost efficient due to their volume
if the design is not that big. On the other hand if you have very big
FPGA the price of silicon area defines the price mostly, and then the
savings can be big.

You have to also divide the NRE+work to each chip, and that also depends
on the process selection.

Habe you looked into eASIC nextreme chips? They should be cheaper than
FPGA and have a low NRE.

> 2) Given VHDL that works on FPGA, will there be considerable risk
> associated with the ASIC conversion?

Yes. There are many caveats at code level. Also IO-structures, PLLs,
clocking, IP-blocks and many other things are different.

As an example initial values in signals work in fpgas, but do not work
in ASICs. ASICs need explicit resets if some initial values are needed.
Also some code structures might be bad for testability (ATPG).

> 3) How long can it take to have working chips?

This depends on the process and design complexity. I would say 9-18
months. You can get even lower if you use some experienced company
for the conversion, the design is not too complex and the process
is not leading edge.

> 4) Who can do it?  Do you have any recommendation?

Just google for companies, one that comes to mind is esilicon, but
there are others. Those companies also look into the business case
and if they are interested in it. If you are in a small company
the ASIC fab might not be interested in the business (too low volume
vs. risk etc.)

--Kim

> >1) Cost savings, how do ASICs compare to FPGAs?
>
> ASICs are very high NRE and low incremental unit cost so to get any
> cost saving at all you have to get a large number of chips made. As a
> first approximation you can assume that you'll have to spend $1M to
> get an ASIC made and say $1 per chip after that.

While the NRE may be this high for <90nm processes, for older
processes it can be a lot less (i.e. less than $100k). So what it will
cost you will depend upon the requirements of your design (i.e. power
consumption, operating frequency, voltage, etc.).

>4) Who can do it?  Do you have any recommendation?

I work for a company who does exactly this job. If you want to discuss
it in more depth, please feel free to drop me an e-mail.

Cheers,
Jon