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Comp.Arch.FPGA | XILINX: verilog is not supported as a language, using usenglish
There are 3 messages in this thread.
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XILINX: verilog is not supported as a language, using usenglish - luudee - 2009-07-02 11:07:00
This should probably go in to the funny error messages folder:
=============== (running make bits within xps) ===============
ChipScope Core Generator command: coregen -b
/home/rudi/reference_designs/ml507_satah/implementation/
chipscope_icon_0_wrapper
/implementation/chipscope_ila_0.xco
ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 10.1 - Xilinx
CORE
Generator K.39 (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
All runtime messages will be recorded in
/home/rudi/reference_designs/ml507_satah/implementation/
chipscope_icon_0_wrap
per
/implementation/chipscope_ila_0_wrapper/coregen.log
Regenerating IP...
Gathering HDL files for chipscope_ila_0 root...
Creating XST project for chipscope_ila_0...
Creating XST script file for chipscope_ila_0...
Creating XST instantiation file for chipscope_ila_0...
Running XST for chipscope_ila_0...
Not generating a VHDL simulation model
Not generating a Verilog simulation model
Skipping VHDL instantiation template for chipscope_ila_0...
Skipping Verilog instantiation template for chipscope_ila_0...
Finished Regenerating.
Successfully generated chipscope_ila_0.
WARNING: verilog is not supported as a language. Using usenglish.
while executing
"error $errMsg"
(procedure "::hw_chipscope_ila_v1_02_a::ila_generate" line 121)
invoked from within
"::hw_chipscope_ila_v1_02_a::ila_generate 94898336"
ERROR:MDT - platgen failed with errors!
make: *** [implementation/sata_host.bmm] Error 2
Done!
================================================================
This is on the Latest Fedora (11) release, x86_64.
Anybody knows where this error is coming from ? Didn't have that
on previous Fedora releases ...
Thanks,
luudee
Re: XILINX: verilog is not supported as a language, using usenglish - Ed McGettigan - 2009-07-03 21:40:00
luudee wrote: > This should probably go in to the funny error messages folder: > > =============== (running make bits within xps) =============== > ChipScope Core Generator command: coregen -b > /home/rudi/reference_designs/ml507_satah/implementation/ > chipscope_icon_0_wrapper > /implementation/chipscope_ila_0.xco > ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 10.1 - Xilinx > CORE > Generator K.39 (lin64) > Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. > All runtime messages will be recorded in > /home/rudi/reference_designs/ml507_satah/implementation/ > chipscope_icon_0_wrap > per > /implementation/chipscope_ila_0_wrapper/coregen.log > Regenerating IP... > Gathering HDL files for chipscope_ila_0 root... > Creating XST project for chipscope_ila_0... > Creating XST script file for chipscope_ila_0... > Creating XST instantiation file for chipscope_ila_0... > Running XST for chipscope_ila_0... > Not generating a VHDL simulation model > Not generating a Verilog simulation model > Skipping VHDL instantiation template for chipscope_ila_0... > Skipping Verilog instantiation template for chipscope_ila_0... > Finished Regenerating. > Successfully generated chipscope_ila_0. > WARNING: verilog is not supported as a language. Using usenglish. > while executing > "error $errMsg" > (procedure "::hw_chipscope_ila_v1_02_a::ila_generate" line 121) > invoked from within > "::hw_chipscope_ila_v1_02_a::ila_generate 94898336" > ERROR:MDT - platgen failed with errors! > make: *** [implementation/sata_host.bmm] Error 2 > Done! > ================================================================ > > This is on the Latest Fedora (11) release, x86_64. > > Anybody knows where this error is coming from ? Didn't have that > on previous Fedora releases ... > A message like this is coming from a language localization routine. It looks like ChipScope core generator is being called from within EDK and somehow verilog was passed as the local language selection instead of an accepted value. Ed McGettigan -- Xilinx Inc.______________________________
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Re: XILINX: verilog is not supported as a language, using usenglish - luudee - 2009-07-04 01:00:00
On Jul 4, 8:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > luudee wrote: > > This should probably go in to the funny error messages folder: > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D (running make bits within= xps) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > ChipScope Core Generator command: coregen -b > > /home/rudi/reference_designs/ml507_satah/implementation/ > > chipscope_icon_0_wrapper > > /implementation/chipscope_ila_0.xco > > ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 10.1 - Xilinx > > CORE > > =A0 =A0Generator K.39 (lin64) > > =A0 =A0Copyright (c) 1995-2008 Xilinx, Inc. =A0All rights reserved. > > =A0 =A0All runtime messages will be recorded in > > =A0 =A0/home/rudi/reference_designs/ml507_satah/implementation/ > > chipscope_icon_0_wrap > > =A0 =A0per > > =A0 =A0/implementation/chipscope_ila_0_wrapper/coregen.log > > =A0 =A0Regenerating IP... > > =A0 =A0Gathering HDL files for chipscope_ila_0 root... > > =A0 =A0Creating XST project for chipscope_ila_0... > > =A0 =A0Creating XST script file for chipscope_ila_0... > > =A0 =A0Creating XST instantiation file for chipscope_ila_0... > > =A0 =A0Running XST for chipscope_ila_0... > > =A0 =A0Not generating a VHDL simulation model > > =A0 =A0Not generating a Verilog simulation model > > =A0 =A0Skipping VHDL instantiation template for chipscope_ila_0... > > =A0 =A0Skipping Verilog instantiation template for chipscope_ila_0... > > =A0 =A0Finished Regenerating. > > =A0 =A0Successfully generated chipscope_ila_0. > > =A0 =A0WARNING: verilog is not supported as a language. =A0Using usengl= ish. > > =A0 =A0 =A0 =A0while executing > > =A0 =A0"error $errMsg" > > =A0 =A0 =A0 =A0(procedure "::hw_chipscope_ila_v1_02_a::ila_generate" li= ne 121) > > =A0 =A0 =A0 =A0invoked from within > > =A0 =A0"::hw_chipscope_ila_v1_02_a::ila_generate 94898336" > > ERROR:MDT - platgen failed with errors! > > make: *** [implementation/sata_host.bmm] Error 2 > > Done! > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > This is on the Latest Fedora (11) release, x86_64. > > > Anybody knows where this error is coming from ? Didn't have that > > on previous Fedora releases ... > > A message like this is coming from a language localization routine. > > It looks like ChipScope core generator is being called from within EDK > and somehow verilog was passed as the local language selection instead > of an accepted value. > > Ed McGettigan > -- > Xilinx Inc. Hi Ed, thanks for your reply. I investigated it a bit further. If I run "coregen -b /home/rudi/reference_designs/ml507_satah/implementation/ chipscope_icon_0_wrapper" from the terminal, it completes without an error. In my environment, I have a variable "LANGUAGE" that is set to an empty string. If I unset it, before starting xps, everything completes without an error. I did a search for that, and it appears to have been a minor bug in the xilinx tools since about ISE 7. Best Regards, luudee