>On Jul 4, 3:19=A0am, "The Lord of
War" <maa105....@gmail.com> wrote:
>> Sadly I'm on my own, and what I'm trying to do is sample an analogsignal
>> save is in digital form in some kind of buffer (here comes the sramrole)
>> and then read it back after some time and convert it back to analog,thus
>> producing a delay that can be controlled. and I need to do long delaysso=
> I
>> nee a big buffer or memory. I checked the xilinx website there is no
>> mention on the use of the onboard ram, so if any one have a lead onthe
>> subject please help, I need to know HOW to do this, a tutorial is goodto=
>o.
>> I'll keep searching and I'll post if I find anything new.
>>
>> regards
>
>Maybe I  missed something, but what board are you using?  Are you
>asking for help with the board you have or ZBT ram in general, or are
>you asking for help with the HDL?  Or maybe all three?
>
>Rick
>

i'm using virtex 4 board 405/6 and on the board is a sram chip and it isZBT,  this sram is on the same board so I need not wire any externalcircuit since the sram module is on the same board, I'm coding using VHDLand all I need to know is HOW can I use this sram module -which is on thesame board :). so HOW e.g. a function call or a built in library with someentity that uses the onboard ram or how can I access this ram?? (what do ineed to do)

thanks in advance

"The Lord of War"
<m...@gmail.com> wrote in message 
news:4...@giganews.com...
> Sadly I'm on my own, and what I'm trying to do is sample an analog signal
> save is in digital form in some kind of buffer (here comes the sram role)
> and then read it back after some time and convert it back to analog, thus
> producing a delay that can be controlled. and I need to do long delays so 
> I
> nee a big buffer or memory. I checked the xilinx website there is no
> mention on the use of the onboard ram, so if any one have a lead on the
> subject please help, I need to know HOW to do this, a tutorial is good 
> too.
> I'll keep searching and I'll post if I find anything new.

The help we give can only be as specific as the information you give us. We 
don't know the sample rate from your ADC; we don't know anything about your 
board; we don't know anything about the synchronous RAM on your board.

Research this:

Find the documentation for your board. Identify the memory device you are 
trying to read and write. Make note of what signals connect to the fpga. 
Identify the pins on the fpga that connect to the memory device.

Find the documentation for the memory device. Make note of the functions of 
the signals connected to the fpga. Make note of the timing information.

You will program the fpga to generate the signals to read and write the 
device. Begin forming in your mind the operations the fpga must perform to 
do this.

You will read and write one or possibly more data words on each ADC sample. 
How many bits in a data sample? How many bits in a memory data word? Does 
the data sample fit in a memory word? Does the sample rate leave enough time 
to read one sample and write a new sample on each cycle?

A ring buffer is suitable for use as a delay line. Define the delay time in 
terms of sample time. For each sample, read the old sample value, and 
overwrite it with the new sample. Advance to the next memory location. A 
modulo-N counter can be used to drive the memory address lines. It counts up 
to N-1 and then starts over at 0.

The memory device has a number of control lines. What are their functions? 
What signals will you drive to read a memory location? What signals will you 
drive to write a memory location?

The ADC sample rate will almost certainly be different from this circuit's 
clock rate. How will you signal the start of a sample period?

Since you didn't ask about the ADC or DAC, I presume you have this part 
under control. The memory is only moderately more complex than reading and 
writing those other devices.

You will also need a one time reset to initialize the ring buffer contents 
to an unobnoxious value. Alternatively, consider just not sending the 
garbage values read during the first delay cycle.

I would go about building things in this order:

Write the HDL for the modulo-N counter. Simulate and verify its operation.

Add the memory control lines. Add this to the simulation and verify its 
operation.

Write a testbench to generate data samples and simulate the memory device. 
Verify the module's operation in the simulator.

Wire the module to your (presumably) already working ADC and DAC modules.

Good luck.

"The Lord of War" <m...@gmail.com> wrote in message 
news:y...@giganews.com...
> >On Jul 4, 3:19=A0am, "The Lord of War" <maa105....@gmail.com>
wrote:
>>> Sadly I'm on my own, and what I'm trying to do is sample an analog
> signal
>>> save is in digital form in some kind of buffer (here comes the sram
> role)
>>> and then read it back after some time and convert it back to analog,
> thus
>>> producing a delay that can be controlled. and I need to do long delays
> so=
>> I
>>> nee a big buffer or memory. I checked the xilinx website there is no
>>> mention on the use of the onboard ram, so if any one have a lead on
> the
>>> subject please help, I need to know HOW to do this, a tutorial is good
> to=
>>o.
>>> I'll keep searching and I'll post if I find anything new.
>>>
>>> regards
>>
>>Maybe I  missed something, but what board are you using?  Are you
>>asking for help with the board you have or ZBT ram in general, or are
>>you asking for help with the HDL?  Or maybe all three?
>>
>>Rick
>>
>
> i'm using virtex 4 board 405/6 and on the board is a sram chip and it is
> ZBT,  this sram is on the same board so I need not wire any external
> circuit since the sram module is on the same board, I'm coding using VHDL
> and all I need to know is HOW can I use this sram module -which is on the
> same board :). so HOW e.g. a function call or a built in library with some
> entity that uses the onboard ram or how can I access this ram?? (what do i
> need to do)

Google on "zbt sram", among the first few hits:
http://www.xilinx.com/support/documentation/application_notes/xapp136.pdf

Also for the same search:
http://www.opencores.org/?do=project&who=zbt_sram_controller

WOW thanks Mike I'll start working on that and
update this post when I findnew stuff.

regards
The Lord of War