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Comp.Arch.FPGA | PLB Master writing to DDR Ram
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PLB Master writing to DDR Ram - gruve5112 - 2009-10-13 21:15:00
Hello, Environment: Virtex II Pro/ Xilinx 9.1i I'm trying to use PLB Master to write on the DDR Ram. I made a C programto make the video frame buffer to read from DDR Ram 0x00000000. Now, I needto make an IP to write on DDR Ram to output something on the video output.I made PLB Master IP to communicate with DDR Ram. In user_logic.v, I'm justassigning IP2Bus_Addr to 0x0 and incrementing it by 64 bits. Whenever theMstWrAck is high, I'm sending some random data like64'h0000_00ff_0000_00ff. However, it doesn't seem to get an access to theram. Can anyone give me any simple example that writes some data from PLB Masterto DDR Ram? Thank you!!______________________________
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