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Comp.Arch.FPGA | Interconnecting 3v3 LVDS transmitter to 2V5 Receiver
There are 3 messages in this thread.
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Interconnecting 3v3 LVDS transmitter to 2V5 Receiver - saijayram - 2009-11-15 08:37:00
Hi. Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..? I am using cyclonII fpga for a receiver in which LVDS inputs are connectedto 2V5 powered bank. will the FPGA be damaged with such interconnection..? I am using these lines for clock (26MHz) interconnecting two boardsseparated by a distance of 6 inches thru mother board. Thank you in advance sai______________________________
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Re: Interconnecting 3v3 LVDS transmitter to 2V5 Receiver - langwadt@fonz.dk - 2009-11-15 09:55:00
On 15 Nov., 14:37, "saijayram" <saijay...@gmail.com> wrote: > Hi. > Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..? > I am using cyclonII fpga for a receiver in which LVDS inputs are connected > to 2V5 powered bank. > > will the FPGA be damaged with such interconnection..? > I am using these lines for clock (26MHz) interconnecting two boards > separated by a distance of 6 inches thru mother board. > > Thank you in advance > > sai shouldn't be a problem, lvds is lvds regardless of what supply voltage the reciever/transmitter is using -Lasse______________________________
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Re: Interconnecting 3v3 LVDS transmitter to 2V5 Receiver - austin - 2009-11-16 11:08:00
Sai, LVDS is a standard. The Vcco is immaterial (does not matter). Yes, they are designed to interconnect (3.3 to 2.5, 2.5 to 3.3). Austin